Surprisingly, the wordline (WL) pitch measured in the bitline (BL) direction was found to be the same as in the previous generation Hynix 44-nm 2-Gbit DDR3 SDRAM, which was measured to be 88 nm. Usually, the technology node for DRAM is defined as the half-wordline pitch. According to the standard definition, the H5TC2G83CFR-H9R device remains at the same node as the previous generation. However, the unit cell of this new device is 40 percent smaller than that of the 44-nm node device.
As seen in the figure below, the process integration scheme is significantly different: The Hynix 44-nm SDRAM has a WL above the Si substrate level and the array transistor employs the saddle-fin structure; the new Hynix SDRAM has a WL below the substrate surface and uses the buried-wordline (bWL) scheme.
Click on image to enlarge.
Figure 1: Unit cell and wordline (WL) pitch, SEM cross-section, in bitline direction. Hynix 44 nm and Hynix 31 nm both have the same WL pitch (88 nm), which by conventional definition implies that the technology node is 44 nm. Hynix 31-nm device uses a buried wordline line integration scheme and has a smaller unit cell than Hynix 44 nm.
Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.
Yes bWl can be extended to 2x node by changing layout to 4F2.
There are some processing issues but 4F2 with bWL is possible.
For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers.
The industry is always looking for other memory alternatives and it will come...
It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready.
What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?
Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node.
In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area.
Cell area will emerge as important criteria for DRAM too.