In hierarchical designs, the quality of the
floorplan is analyzed after the blocks are integrated at the top level.
This can result in unnecessary iterative work, wasted resource hours,
and longer cycle times, which could mean missed market opportunities. As
technology trends towards smaller nodes, the sizes of the standard
cells decreases but pin count remains the same. So if we want to close
designs with higher utilization, to save on die area, we will end up in a
situation of routing congestion somewhere in the design. The proper
estimation of utilization is very important and difficult at the initial
stage, as this depends upon various factors such as frequency, power
saving technique and gate count. Even after putting efforts into
planning, there is some weakness left in the design process, which will
lead to late stage surprises including routing congestion. We’ll cover
two cases which generally become show stoppers in terms of top-level
signal routing congestion in a design, once placement and routing for
sub-partitions is closed and top-level placement is also closed with
respect to timing.
Consider a scenario where
two partitions at the top level need to be placed side-by-side (shown in
figure 2). Partitions A and D are being placed side-by-side.
Figure2: Signal routing congestion due to higher utilization
D is directly interacting with both the pad ring, to communicate with
the external world, and internally within the chip. In order to
communicate with the pad ring, pins for partitions “D” interacting with
the external world need to be placed on the top or left side (shown in
the figure 2). Pins interacting with the top-level Sea of Gates (SoG)
are placed on the right side for better timing.
Partition A also
needs to interact with the top-level SoG, so for better SoG interaction,
the best position for pin placement is at the bottom side of the
partition A (shown red in figure2).
With such a scenario,
top-level gates interacting with both the partitions should be pulled
toward the boundaries of the partitions to meet the timing specification
and results in high placement density in the area shown in green. This,
however, will lead to signal congestion. The traditional way to solve
this issue is to increase the resources at the top level by shrinking
the dimensions of the sub partitions. If this is performed late in the
design cycle it will result in product delay. Decreasing the dimension
of sub-partition creates a need to close the partition from scratch,
which is a knotty task and also require extra resource for sub-partition
Consider a scenario where two
partitions are placed as shown in figure 3. Partition E, acting as the
heart of the system, is small and interacting with almost every
partition in the design. This requires it to be placed in the center of
the design, so that sub-partitions have easy access to it. When
partition E is placed on the right of partition C it only overlaps a
small portion of partition C, so some buffering channel is required for
the pins of partition C in the area that is covered by partition E to
meet the timing requirement for the pins.
Figure 3: Signal routing congestion due to high pin count
placement for the top-level SoG, both partitions C and E generally try
to get placed closer to the pins, to meet timing specifications. The
designer may try to restrict the placement to avoid routing congestion.
Even then, routing congestion arises on the notches of partition E, due
to the high pin count of the cell. In order to close this issue the
designer needs more resources in terms of area and routing. This will
again require an iterative process of shrinking block sizes to free up
some area for the top level and re-do the block closure activities from
scratch with decreased dimensions.