The road to DesignCon 2013 is paved with the technology labors of past shows.
To whet your appetite for this year's edition, we bring you an important paper from a past show. It's entitled "What, if anything, in SystemVerilog will help me with FPGA-based designs?"
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes attendance at a dozen tech training sessions.]
The downloadable paper is authored by EDA expert Stuart Sutherland, of Sutherland HDL, which trains engineers in using SystemVerilog. Stuart is also a member of the IEEE SystemsVerilog standards committee, so you doubly know he knows his stuff.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.