Effective area feature size (Feff) and physical feature size (Fphys)
3D NAND cell architectures can be categorized into a vertical channel 3D NAND  and a horizontal channel (vertical gate) 3D NAND  (see figure 9). Both architectures have a physically large cell size, mainly due to a wider channel width, while it is smaller in effective area due to the stacking of multiple tiers.
Figure 9: 3D NAND architectures and parameter assumptions.
Table II summarizes key feature size definitions for 3D NAND. A cell stack thickness (pillar to control gate distance) and a tier thickness are kept constant in this analysis.
Figure 10 shows a relationship between the physical feature size and the effective area feature size for 3D NAND. The cell architecture and the process parameters should be defined so that Fphys
are best balanced.
Figure 10: Effective area feature size and physical feature size
relationship. The vertical 3D NAND can have a larger physical
cell size, which is advantageous for cell properties, while
the horizontal 3D NAND can have fewer tiers.
The wider channel width and shorter string length of the vertical NAND enhances string conductance, which is advantageous for sense operation (see figure 11). Poly-channel mobility should be engineered to maintain this advantage. The poly-channel mobility requirement becomes more stringent as the number of tiers increases for the vertical NAND. The string conductance is more challenging for the horizontal NAND due to the lack of the gate all around structure. However, the number of tiers can be increased without impacting the string conductance in the horizontal NAND.
Figure 11: String conductivity scaling for 3D NAND. The string
conductivity is normalized by channel width and string length.
The vertical NAND is advantageous for the string conductivity
due to the gate all around structure.
A near-vertical pillar profile is a key to achieving effective cell area scaling over 2D NAND. With a tapered pillar profile, the effective area scaling benefit from a tier stack diminishes due to a larger cell foot print at the top tier (see figure 12).
Figure 12: Etch taper angle and effective area feature size
Vt placement width
relationship. The effective area scaling benefit from
the tier stacking diminishes with a tapered etch profile.
Figure 13 shows Vt placement width scaling. Due to the increase of cell noise (interference, RTS and statistical fluctuation), the raw Vt placement widens with 2D NAND scaling. Enhanced error correction, system and algorithmic solutions are required to maintain the same effective Vt placement width. The large physical cell size of 3D NAND is advantageous for the cell noise and the placement width. However, 3D NAND process could introduce other sources of noise such as RTS degradation [9-10] or poor data retention. This diminishes the physical cell size advantage of 3D NAND. Therefore, 3D NAND process integration needs to be engineered so that a net gain is achieved in the effective Vt placement width over 2D NAND.
Figure 13: MLC Vt placement width (±3?) scaling. 3D NAND cell
is advantageous due to the larger physical cell size.
The planar FG cell is the best solution for 2D NAND scaling as it overcomes many structure and reliability limitations of scaling. After the 2D NAND hits a scaling limit due to the increase in cell noise and WL-WL E-field, NAND scaling can continue with the 3D NAND. The key to 3D NAND cell scaling is cell architecture definition to maximize the physical cell size while minimizing the effective cell area. Cell noise reduction by the large physical cell size and successful process integration is critical to realize tight Vt placement and excellent reliability for the 3D NAND.
The authors gratefully acknowledge the Intel-Micron IMFT NAND team and the TCAD team.
1. K. Parat, VLSI-TSA, pp. 101-102, (2009).
2. K. S. Seol, et al., VLSI Tech Symp. Digest, pp. 127-128, (2010).
3. T. Yaegashi, et al., VLSI Tech Symp. Digest, pp. 190-191, (2009).
4. Y. Park et al., IEDM Technical Digest, pp. 2.1.1-2.1.4, (2006).
5. A. Torsi et al., IEEE TED vol. 58, no. 1, pp. 11-16, (2011).
6. K. Prall and K. Parat, IEDM Technical Digest, pp. 5.2.1-5.2.4, (2010).
7. H. Tanaka et al., VLSI Tech Symp. Digest, pp. 14-15, (2007).
8. W. Kim et al., VLSI Tech Symp. Digest, pp. 188-189, (2009).
9. E. Nowak et al., VLSI Tech Symp. Digest, pp. 21-22, (2012).
10. M-K. Jeong et al., VLSI Tech Symp. Digest, pp. 55-56, (2012).