Some product topologies are not suitable for this burn-in method, such as those that have a poorly defined or strongly re-entrant short-circuit current characteristic. For example, if on a “hard” short circuit the output current reduces to much less than the rated maximum output current or if the supply enters a “hiccup” mode, the level of burn-in stress may be too low to be effective.
The decision on burn-in configuration is made jointly between design and reliability/quality engineers to ensure optimized screening. Data logging and analysis of the units under test is important for determining whether and when a failure has occurred. If all failures occur in the first few minutes of a 48-hr burn-in sequence, there would be good reason to shorten the time and increase throughput while saving energy.
A comprehensive test after burn-in is necessary to ensure that products are fully functional. This can also show whether there are any intermittent problems. Understanding and using burn-in data to modify product design and manufacturing processes can result in improved reliability and yield so companies like Murata Power Solutions use burn-in data to drive a continuous improvement quality process.
Experience in burn-in testing has shown that thermal cycling precipitates more infant mortalities than a constant elevated ambient although the sets of failures don’t completely overlap. Thermal cycling with a dwell time at each thermal extreme is therefore the preferred process. Increasing the rate of change of burn-in temperature precipitates more failures in fewer cycles as illustrated in Figure 2.
Note that with increased thermal rate of change, different populations of failures can appear that are more or less affected by this type of stress and the occurrence of some residual failure types is unaffected. Even though there is equipment available to achieve thermal rates of change of 60°C per minute or higher, some manufacturers don’t exceed 45°C per minute to prevent excessive thermal stress that may, for example, cause cracking of multilayer ceramic capacitors (MLCCs).
In the absence of thermal cycling chambers, power cycling at an elevated ambient with judiciously selected cycle times approaches the effectiveness of the thermal cycling/dwell process. Care must be taken to ensure that the products are not stressed outside of their ratings in the often atypical environment of burn-in. If overstressed, significant useful life of a good product could be used up, and at worst, hard or latent failures could actually be induced in otherwise good product. If the product includes components with inherent wear-out mechanisms such as electrolytic capacitors or optocouplers, their remaining lifetime after burn-in should be evaluated to be adequate.
At Murata Power Solutions, the burn-in process typically starts with a duration of 24 hours, with a decision process to reduce the burn-in time when no failures occur after a set number of hours. Standard IPC-9592 gives plans for reduction of burn-in times given observed failure rates over set number of unit-hours.
Burn-in can be eliminated when no failures occur after multiple production builds. However, it could be argued that this removes the insurance against a group of defective components being used or a process anomaly occurring. In volume production of parts that are known to have a significant infant mortality rate, perhaps because of the degree of manual assembly, a regime of variable burn-in can be implemented whereby burn-in is terminated when a pre-calculated period of failure-free operation of a batch has passed.
This period is found from statistical tables, given the expected percentage of infant mortalities, their known failure rate and distribution type, batch size and percentage confidence level required that only a given number of latent failures remain. For example, consider a batch of 10,000 units that historically has had 10 infant mortalities per batch of a type found to have a mean time to failure (MTTF) of 10 hours at the burn-in temperature. In this case, statistical tables show that a failure-free period of 13 hours must pass to give a 90-percent confidence level that only one latent product failure remains. The period extends to 24 hours to have the same 90 percent confidence level that no latent infant mortality-type failures remain. (Reference 1)
Some manufacturers have taken the burn-in process further after finding that the types of burn-in described do not eliminate, within a reasonable time, all of the failures occurring in the early life of a power supply. Also, conventional burn-in does not provoke early failures that could be a result of the shock and vibration of shipping and handling.
To combat this, a more aggressive highly accelerated stress screen (HASS) can be used that applies mechanical, thermal and electrical stress typically beyond product ratings but within design margins. Acceleration factors of more than 40 over conventional burn-in have been claimed for this method, giving correspondingly shorter test times.
A problem, however, is that the stress levels are so extreme there is a risk of damaging good product with hard or latent failures. In answer to this, the highly accelerated life test (HALT) process was designed to identify the real damage limits in a product by stressing the product to failure with temperature extremes, thermal cycling, progressively higher levels of vibration, and then a combination of thermal cycling and vibration.
During this testing, the destruction limits of the power supply are identified. These operating limits are then used to set the less-severe HASS test levels. HALT is also used extensively during product development to identify potential weaknesses in the design. The test equipment required to do HALT must typically ramp temperature between -55°C to 125°C while applying six-axis linear and rotational random vibration. This requires a major capital investment and is often subcontracted to specialist test houses. Some vendors such as Murata Power Solutions already have internal HALT facilities.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.