The LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture developed by Aeroflex Gaisler AB in Sweden. The model is highly configurable and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.
The LEON project was started by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects. The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost.
- No licenses are required for research and education use.
- All RTL source code is available
- Fast support
- Linux and RTOS can be installed
- Not all FPGA development boards are supported.
- Not in widespread use
The complete design environment for the LEON3, including all the IP cores, can be downloaded from the Gaisler Aeroflex webpage (www.gaisler.com). The AMBA-2.0 AHB/APB bus has been selected as the common on-chip bus due to its market dominance (ARM processors) and because it is well documented and can be used for free without license restrictions. The LEON3 can be easily configured using a graphical user interface.
to check out the entire LEON3-based design process in my blog.