LONDON – Samsung Electronics Co. Ltd. has launched an eight-core ARM-based processor that uses the big-little processing technique announced by ARM Holdings plc in 2011. The announcement was made by Stephen Woo, Systems LSI president of the Samsung during a keynote presentation at the Consumer Electronics Show being held in Las Vegas.
Woo said the Exynos 5 Octa is the world's first mobile application processor to implement the big-little processing strategy. The chip has a quad-core Cortex-A15 processor optimized for high performance and a quad-core Cortex-A7 processor that is optimized for lowest power operation.
The Exynos 5 Octo is a follow-on to the Exynos 5 Dual, which is already designed into products including the Google Chromebook and the Samsung Nexus 10 tablet.
Samsung did not indicate in what manufacturing process technology the Exynos 5 Octo is implemented or the highest clock frequency or lowest voltage operation of which the chip is capable.
In a statement issued by Samsung Woo described the Exynos 5 Octa as the "best application processor currently available." It is a claim for which there is much competition.
At CES Qualcomm has announced the Snapdragon 800 quad-core processor, Nvidia has announced the Tegra 4 and ST-Ericsson the NovaThor L8580 ModAp. Both the Snapdragon and NovaThor parts have an LTE modem integrated with the application processor.
Warren East, CEO of ARM, joined Woo on stage and helped introduce the big-little technology that debuts in the Exynos 5 Octa. The application processor provides up to 70 percent higher energy efficiency than the previous quad-core Exynos.
Samsung did not disclose what process technology is being used for the Exynos 5 Octa, nor what graphics processing unit has been selected. The previous generation Exynos 4 Quad and Exynos 5 Dual are both made using 32-nm CMOS and include quad-core Mali GPUs, also licensed from ARM.
There is speculation that the Octa chip is implemented in 28-nm CMOS and that the quad-core Cortex-A15 runs at up to 1.8-GHz and the Cortex-A7 cores run at 1.2-GHz. Similarly it is thought that the GPU is the ARM Mali-T604 quad-core
GPU used in the Exynos 5 Dual, with the two chips also likely to
share the same 32-bit dual-channel 800MHz memory controller with its
DDR3 and LPDDR3 memory support and peak 12.8GB/s bandwidth.
If the Exynos 5 Dual is a guide the Octa will have a dual channel 32-bit memory interface capable of 800-MHz LPDDR3/DDR3 or 533-MHz LPDDR2 capable of 12.8-Gbyte per second and 8.5-Gbyte per second bandwidth respectively.
You're right, but I doubt all cores will be used except for very specific applications meant to take advantage of it - like any app that could take advantage of heterogeneous computing.
The rest 99.9% of them will only use 4 cores at most.
Well, that has to be the main application target, isnt't it? If Samsung wanted to have just more power, they would have not bothered with the big-little implementation. They would have used eight full-speed, full-power cores, all active at the same time and with the usual clock scaling. This seems to be a sensible compromise, two distinct, selectable computational levels, each optimized for different operational conditions, plus the option to combine both to have higher processing power when really needed.
Thanks for information for Nvidia Core.
I am surprised that my comments cause so much discussion. I will agree that nothing prevent all 8 cores running at the same time although it is not likely choice. A7 performance per MHz is only half of A15 and is running at 60% of clock frequency. Therefore, each A7 core will only deliver 1/3 A15 performance. So it doesn't make lots of sense to allow A7 join A15 cluster in most cases. Therefore, its performance is only equivalent to 5.3 A15 Core performance. So we should call Samsung 5.3 Core in the future. :-)
You bet they can! Think real-time image/data processing and data collection tasks. I have applications that consume all of my dual-core processing right now and could use more. The issue, now, is power consumption (how long can I run on all four cores going at full speed) and memory bandwidth (can my portable device's memory feed all those processors fast enough to keep them running at full speed).
My understanding is that in standard big-little operation the operating system sees just four cores.
As load increases applications move up through the dynamic voltae and clock frequency scaling (DVFS) on the A7 until it is close to maximum then they are moved on to the low-end of the DVFS for for the companion A15 where the scaling continues to maximum voltage and clock frequency. As the processing load reduces the reverse happens.
There is not much latency in switching from A7 to A15 but it is still important to avoid a hysteresis effect where the software repearedly bounces from A7 to A15 and back.