In the automotive industry, reliability and high quality are key attributes for electronic automotive systems and controls. It is normal for these automotive applications to face high operating voltages, and high electric fields between nets that can lead to oxide breakdown. Moreover, electrical fields can influence sensitive areas on the chip, because high-power areas (60V, 80V, 100V, etc.) are commonly located next to logic areas (1.8V, 5V, etc.). Consequently, when designing and verifying many smart power processes, designers must deal with metal spacing design rules that are dependent on voltage drop. For example:
- Metal2 minimum spacing can be x if voltage drop across lines is up to 30V, and it will be y if voltage drop across lines is up to 80V. Where y > x, similar rules apply for the rest of the metal layers.
- Minimum spacing between metal and poly is x where voltage difference is higher than V volt.
- Shapes on a specified metal layer canít cross a specified area, based on the voltage difference.
- It is not allowed to cross an adjacent metal level if voltage drop is higher than V volt.
Trying to implement such rules in the entire design flow, starting from layout routing implementation through design rule checking (DRC), is too conservative, as well as inefficient, due to lack of voltage information on nets (both in schematic and layout). Trying to achieving this goal with traditional exhaustive dynamic simulation is simply not practical, due to the turnaround time involved, and, if the design is very large, it may not even be possible to simulate it in its entirety. Design teams need a way to determine the voltages at all internal nodes statically. Advanced EDA solutions that can quickly and accurately evaluate customized electrical requirements can help designers achieve their goal of generating the proper net voltage information in an efficient static way.
New circuit reliability verification tools provide a voltage propagation functionality that can help perform voltage-dependent layout checks very efficiently while also delivering rapid turnaround, even on full-chip designs. In addition, they provide designers with unified access to all the types of design data (physical, logical, electrical) in a single environment to enable the evaluation of topological constraints within the context of physical requirements. Letís look at some examples, using Calibreģ PERCô to demonstrate the basic functionality.