In order to achieve the high throughput requirements of a USB 3.0 system, it is required to be able to perform data transfers between the various peripherals without intervention of the CPU. This can be achieved through a Direct Memory Access (DMA) controller for communication between various blocks.
For example, consider a decentralized DMA system; i.e. there is no central DMA controller. This means that each DMA-capable interface will have its own DMA adapter. DMA transfers occur between a producer and consumer over logical entities called sockets. The producer socket fills a buffer pool in common memory with data. When one buffer is filled, it updates the buffer descriptor to indicate that the buffer is filled and notifies the consumer socket. The producer socket then switches to the next buffer in the buffer pool. This is continued until all the buffers are filled. After that, the socket will be suspended until a buffer is available. Upon receiving the notification from the producer that a buffer is full, the consumer socket empties the buffer. It then updates the buffer descriptor to indicate that the buffer is empty and sends a notification to the producer socket. The consumer socket then switches to the next buffer in the buffer pool. This is continued until all the buffers are empty. Thus synchronization is achieved between the producer and consumer along with faster data transfer across the DMA channel.
Figure 5: Decentralised DMA architecture
General-purpose parallel interface.
A USB 3.0 controller should have a 32-/16-/8-bit parallel interface for communication with various external application processors such as image sensors, FPGAs, ASICs, etc. The interface should operate at a high frequency of 50-100 MHz to provide the required throughput. Communication between a USB 3.0 controller and an external application processor over a general-purpose parallel interface is as shown below:
(a) Application processor acts as master
When the application processor is an intelligent system such as a DSP, then the USB 3.0 controller can act as a slave with the application processor providing the control signals for read/write operations.
Figure 6: USB 3.0 controller interfaced to a master processor
(b) Application processor acts as a slave
When interfaced to a non-intelligent application processor, the USB 3.0 controller will act as master to provide the required control signals for the interface as shown below:
Figure 7: USB 3.0 controller interfaced to a slave processor
The FX3, used as an example, is a USB 3.0 peripheral controller, which can be used to implement a USB 3.0 interface in multiple applications such as imaging, data logging, etc.
It provides a 32-bit general programmable interface (GPIF), which can operate at frequencies up to 100MHz. The GPIF registers may be configured by generating a state machine created using a user-friendly GPIF II designer interface. The GPIF II designer also provides several templates for common interfaces such as slave FIFO, sync AdMUX, etc. so that the user can easily modify them as required for a particular application. Also included are such features as USB 2.0 OTG and serial peripherals like UART, SPI, I2C, and I2S. The FX3 DMA can also be easily configured for a variety of applications. It is easily integrated into image sensor or FPGA interfaces.
The addition of a USB 3.0 controller to an existing application provides a straightforward way to upgrade a system to SuperSpeed without requiring too many changes in the system. This not only improves the maximum data rate but also increases device functionality and flexibility.