PORTLAND, Ore.—Today's analog and mixed-signal (AMS) design flows can make use of behavioral models to streamline development, but not for every element of a design. Engineers need to mix-and-match their AMS modeling techniques, choosing device-level simulators for the most critical portions, leaving the high-level description languages for non-critical segments of a design.
Verilog-A was the first standard high-level design language capable of verifying analog circuits without losing accuracy compared with old-school Spice. From the beginning, however, the plan was always to follow-up by coupling the analog and digital domains, so that events in either could trigger events in the other. The result was Verilog-AMS, with which engineers can simulate, verify and create high-level behavioral descriptions of even the most complex analog, mixed-signal and radio frequency (RF) circuits.
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The tradeoff is accuracy over speed. Spice simulations, for instance, not only provide the ultimate accuracy of transistor-level precision, but also model undesirable effects, such as parasitic capacitance. But that takes time. Spice is also routinely used in lengthy and slow-running Monte Carlo simulations that allow a range of circuit values, manufacturing tolerances, and component variations to be simulated with regard to their affect on performance.
Verilog-A, on the other hand, enables engineers to use a design language to create accurate continuous-time analog simulations. And Verilog-AMS extends that modeling language into the mixed-signal domain. In practice, Verilog-AMS was actually derived from the full Verilog hardware description language (VHDL) by adding analog and mixed-signal extensions to its event-based simulator loops. As a result, today engineers can pick-and-choose the right tool for the right job--from device-level details to very high-level behavioral modeling capabilities that streamline the design process.
As a rule of thumb, many designers use behavioral modeling for the digital parts of a mixed-signal circuit, but refine their models with blocks that require more accurate analog representations. There are also many tools that give designers best practices and current and future usage of various modeling styles, such as IBIS (input/output buffer information specification) which can be used in lieu of Spice to allow detailed modeling and verification to be performed without revealing the intellectual property used to implement a design.
"Attendees to our tutorial will achieve a better understanding of analog and mixed signal modeling in general," said session-chair Thibieroz. "Then on the panel the next day, attendees will explore the pros, cons, challenges and limitations of each approach as it applies to real world design problems."
Thibieroz will moderate the DesignCon panel titled "Behavioral Modeling for Analog, Mixed-Signal, and RF: What is the Best Approach Today?" on Tuesday, Jan. 29, from 3:45 to 5:00 pm in Ballroom E. Related links:
It was indeed a great panel. I had panelists from various background experts in their areas sharing their opinions on various questions pertinent to behavioral modeling- from IBIS/IBIS-AMI to VerilogAMS and real number modeling. The panel was really well received and there was a lot of interesting reactions in the audience. I will generate a summary because some of the questions that I asked triggered really interesting responses. Regarding your comment, there is definitively a push to move the simulation entirely in the digital space. However, I do believe, that depending of what your end goal is (functional verification/ first path or need for more analog accuracy), simulating only using a digital solver (using behavioral verilog or real number modeling) may not be enough and you may have to deal with a mixed flow.
I bet this was a great panel discussion. Wish I could've attended.
BTW, as cool as Verilog-AMS is, it is still awfully slow for a transient simulation with a lot of high frequency events. For chip-level verification of an AMS IC, we have had good results just modeling analog blocks in behavioral Verilog. You can make those models as simple or as detailed as you like, and still maintain essentially the same fast simulation times as a pure digital Verilog RTL simulation.
I think that you meant to say that Verilog-AMS was derived from the IEEE 1364 Verilog HDL specification, however your article says it was derived from VHDL. http://www.accellera.org/activities/committees/verilog-ams/about/
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.