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Stars of DesignCon: Behavioral modeling aids analog/mixed-signal

1/28/2013 08:01 PM EST
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hthibieroz
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re: Stars of DesignCon: Behavioral modeling aids analog/mixed-signal
hthibieroz   2/28/2013 5:36:57 PM
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Hello, I wrote a summary at http://bit.ly/WjRxZT

hthibieroz
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re: Stars of DesignCon: Behavioral modeling aids analog/mixed-signal
hthibieroz   1/31/2013 4:51:20 PM
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Frank, It was indeed a great panel. I had panelists from various background experts in their areas sharing their opinions on various questions pertinent to behavioral modeling- from IBIS/IBIS-AMI to VerilogAMS and real number modeling. The panel was really well received and there was a lot of interesting reactions in the audience. I will generate a summary because some of the questions that I asked triggered really interesting responses. Regarding your comment, there is definitively a push to move the simulation entirely in the digital space. However, I do believe, that depending of what your end goal is (functional verification/ first path or need for more analog accuracy), simulating only using a digital solver (using behavioral verilog or real number modeling) may not be enough and you may have to deal with a mixed flow.

old account Frank Eory
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re: Stars of DesignCon: Behavioral modeling aids analog/mixed-signal
old account Frank Eory   1/29/2013 7:47:00 PM
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I bet this was a great panel discussion. Wish I could've attended. BTW, as cool as Verilog-AMS is, it is still awfully slow for a transient simulation with a lot of high frequency events. For chip-level verification of an AMS IC, we have had good results just modeling analog blocks in behavioral Verilog. You can make those models as simple or as detailed as you like, and still maintain essentially the same fast simulation times as a pure digital Verilog RTL simulation.

Daniel Payne
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re: Stars of DesignCon: Behavioral modeling aids analog/mixed-signal
Daniel Payne   1/29/2013 4:25:21 PM
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I think that you meant to say that Verilog-AMS was derived from the IEEE 1364 Verilog HDL specification, however your article says it was derived from VHDL. http://www.accellera.org/activities/committees/verilog-ams/about/

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