LONDON – Chip packager Stats ChipPac Ltd. and foundry United Microelectronics Corp. have demonstrated a 3-D stacked chip made using through-silicon vias (TSVs) and developed under an open ecosystem collaboration.
The 3-D chip stack comprises a Wide I/O memory test chip stacked on top of a 28-nm processor test chip with embedded TSVs. Stats ChipPac and UMC did not reveal the processor type or the source of the Wide I/O die.
Under the 3D-IC development project with Stats ChipPac, UMC provided the front-end of line wafer manufacturing with a 28-nm polysilicon silicon oxynitride gated process that includes TSVs.
The know-how developed will be applied for implementation on the foundry's 28-nm high-K metal gate (HKMG) process, the companies said. For MEOL and BEOL, Stats ChipPac performs the wafer thinning, wafer backside integration, copper pillar bumping and chip-to-chip 3-D stacking.
"We see no imperative to restrict 3-D IC to a captive business model, as UMC's development work with nearly all the major OSAT [outsourced semiconductor assembly and test] partners for 3-D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach," said S.C. Chien, vice president of Advanced Technology Development at UMC, in a statement issued by Stats ChipPac.
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