PORTLAND, Ore.—Texas Instruments Inc. (TI) unveiled a plethora of systems-on-chip (SoCs), software and reference designs for smarter-grid and -meter applications at DistribuTECH 2013, a smart grid conference and exposition for the utility industry. More 60 new SoCs provide what TI claims is best-in-class accuracy, integrated memory and built-in smarts including anti-tapering prevention.
The new family of SoCs (MSP430F677x) have an enhanced analog front end with up to seven 24-bit sigma-delta data converters, meets the regulatory requirements for smart meters worldwide (IEC 62053-22 and ANSI C12.20) plus includes ease-of-use features such as dynamic pricing tables, large buffers for readings, smart communications stacks for all networking protocols (ZigBee, wM-Bus, G3-PLC, RF Mesh), tampering detection and conformance to both the Device Language Message Specification (DLMS) and the Companion Specification for Energy Metering (COSEM).
TI also supplies its free MSP430 Energy Library code with built-in algorithms for all the polyphase meter calculations of energy usage and power consumption as required by the ANSI/IEC worldwide standards. TI also showed two new reference designs at DistribuTECH (Jan 29-31, San Diego). Its Smart Data Concentrator Evaluation Module includes pre-written code for TI's integrated ARM Cortex-A8 that performs data concentration functions for up to 1000 smart meters. And its Home Gateway Reference Design provides the ARM code to connect ZigBee, WiFi or Ethernet networks to home automation systems controlled by smartphones or tablet apps.
TI's smart grid SoCs, software and reference designs enable in-home displays to equip consumers with information that enables them to control of their energy usage.
Developers can easily plug in different connectivity modules, including sub-1GHz low-power RF (LPRF), general packet radio service (GPRS), near field communication (NFC) or TI’s own power-line communication (PLC) system-on-module (C2000 Piccolo F28PLC83) using its advanced AFE supporting a variety of networking protocols (PLC-Lite, PRIME, G3, IEEE-P1901.2).
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.