Today’s complex systems employ a wide variety of semiconductor technologies. From the deepest sub-nanometer processors to the analog I/O, it’s easy to see the need for power management devices for multiple voltages – 1.0V, 1.2V, 1.5V, 1.8V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V and more – all in the same box.
Dozens of companies offer thousands of chips to address these needs. Data sheets, PDKs and application notes make implementation easier than ever. If your volume is high enough, chip company application engineers are more than willing to do the design work for you. Sit back, watch YouTube, follow friends on Facebook and wait for the circuit to arrive by email. It’s not quite that simple, but let’s be honest, there are a lot of free resources out there to assist.
A few dozen years ago, engineers fresh out of school were assigned to the power supply team; the most boring and least challenging aspect of the system and the one most forgiving of inexperience. Could it come to that again?
Not likely. But you really should ask yourself, who is really managing your power management. Is it you or your suppliers? Who really understands your power management needs and more importantly, the solution you’ve implemented? Is your 7Amp 1.2V solution overkill for your 2.9Amp requirement? Could a lower cost LDO be used instead of that switcher?
“Gee, thanks Mr. Semiconductor Company Applications Engineer for designing most of my system with all your high margin chips. It sure plays nice in my application.”
Power management is more than developing solutions that run cool and conserve power. It’s also about managing cost. With today’s plethora of fifteen and twenty cent chips, it’s easy to assume your design is financially viable. But is it?
Financial management is inextricably intertwined with power management. Often power management solutions transcend multiple product generations. It’s the most logical place to drive cost out of a system for greater long term savings. Yet, for some reason, it’s also the most overlooked.
The following figure represents the power board for a typical consumer application:
Depending on total volume, the bill of materials may range from $1.00-$1.50 at the low end, to perhaps as high as $2.00.
However, integrating these seven chips into what is called an iASIC, or integrated ASIC, would yield a much lower cost single chip solution while retaining all the desired power saving functionality of the original designs. An iASIC (a chip integrating existing functions without the need to create new IP) is easy to accomplish and has a short development time.
The cost of the iASIC for the above set of requirements would be in the neighborhood of $0.60 each.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.