Editorís note: This work was first presented at the 2012 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE. For more information about IEDM 2013 (Washington DC; December 9-11), click here.
Abstract We demonstrate an 8-layer 3D Vertical Gate NAND Flash with write line (WL) half pitch =37.5nm, bit line (BL) half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BLís (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices  and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.
Introduction 3D stackable NAND Flash is forecasted to continue NAND Flash scaling below 15nm node . In general, 3D NAND Flash uses minimal processing steps to pattern the multi-layer stacks only once, thus greatly reduces the bit cost. However, most 3D NAND architectures have relatively larger lateral half pitch (>60nm ) due to many limitations. The large cell pitch must be compensated by very large stack number (>32) in order to compete with sub-20nm 2D NAND. This greatly reduces the bit cost advantage and threatens the future prospect.
3D vertical gate (VG) architecture [1,4-6] was considered as the most pitch scalable 3D NAND architecture. Like conventional NAND, it uses WL/BL patterning thus the lateral pitch can be scaled in a similar way as conventional 2D NAND. However, the decoding method for 3DVG NAND is more difficult than the vertical channel (VC) NAND  because the BLís are horizontal, parallel to the multi-layers and thus cannot be simply connected to metal BLís as in the conventional 2D NAND.
The first proposed VG architecture uses plural rows of normally-on SSL devices  to decode the BLís within the NAND string. As the stacked layer increases, the required row number of SSLís increases accordingly, greatly reduces the array efficiency. Later, an island-gate SSL device [1,5] was proposed to separate channel BL for decoding, as shown in Fig. 1(a). This avoids the issue in  and the array efficiency can be kept constant as stack layer increases. However, fabrication of the island-gate SSL within each channel BL is difficult when BL pitch is scaled.
Click image to enlarge.
Figure 1: (a) Previously proposed 3D Vertical Gate (3DVG) NAND architecture . Island-gate SSL is used to separate channel BLís, while staircase BL contacts are used to decode the memory array. The island-gate SSL has the same pitch as the channel BL, thus makes BL pitch scaling difficult. (b) 3D overview of the proposed Twisted BL (Split-page) VG architecture in this work. We split the even/odd island gate SSL in the opposite direction, allowing island-gate SSL devices be laid out in double pitch, providing much larger process window for BL pitch scaling.
The WL's and BL's are not individual lines but linked within the same plane, forming forks. The BL fork actually touches source line, not actual fork shape sorry. Voltage over entire plane being same, the capacitive coupling to neighboring plane is serious risk.