It is clearly evident that doing a
cycle-based evaluation for each condition of the power table for each
cell in a design is not a scalable solution for large SoCs. So instead
of taking a purely probabilistic approach, or a complete cycle-based
approach, power analysis flows can take a hybrid approach depending on
the following factors:
- Stage of the design, including availability of the RTL or netlist, or libraries for hard macro
- Availability of simulation data
- Design specific data – like memory, datapath, analog cells, black boxes, etc.
Figure 1: A typical early stage IP sub-system block
Suppose we have a design at an early stage of RTL coding. As shown in Figure 1, there are 4 blocks:
Block A: This is an RTL block for which simulation data is available.
Block B: This is an RTL block for which no simulation data is available so far.
C: This is a black box for which the RTL is still not available, but
the designer is aware of some characteristics of this block.
Block D: This is block primarily consisting of memories and we have a simulation output file for this block.
we can see, there is a fair variation in the progress and the
characteristics of each block. Also, each block is at a different stage
with respect to the availability of simulation data. So the early power analysis flow should be able to handle the best information available.
A has RTL with simulation data information. So the power analysis tool
should be able to accept a simulation file at the block level. Since
this block is mostly standard cell logic, power analysis tools will
consume a VCD or FSDB data and convert it into toggle counts and duty
cycles for each net. This will ensure that power estimation is much
faster than a cycle-based approach. The error introduced here because of
the loss of spatial and temporal correlation will not affect the
accuracy of results for this kind of a design.
B is also an early stage RTL design where the simulation data is still
not available. But at this stage, the designer has some information
regarding the critical signals. These will be clocks and control
Here, we can specify the clock period of the clock and the activity information or toggle rate for critical signals.
times, it is hard to specify the toggle rate for a signal internal to
the design. However, even for vector-less power estimation, capturing
the information for such signals is important. So the flow should allow
specifying toggle information on such signals. One such signal is clock gating enables for blocks or registers.
C is a black box. There is no RTL information. So for such a case, the
flow should be able to capture coarse design information, as shown
below, in an early power analysis tool such as Atrenta’s SpyGlass®
blackbox_power -instname block_c -equiv_nand2_count 3000 \
-register_count 100 –activity 0.3 -clocks a1 a2 -clock_percentage 0.5 0.5
above command in the power analysis tool specifies that the black box
will contain 3,000 NAND gate equivalent cells and 100 registers. Also,
the average activity of this module will be 0.3. With this information
and technology libraries the flow can estimate the power of this black
Block D contains many memories.
Earlier in this section, we have seen that memories have a very high
variation of dynamic power based on different access operations like
“read” and “write”. So for this block, we need very accurate power
estimation. A robust power estimation flow should be able to identify
such logic from other logic in the design. Once it identifies such
cells, it will enable very accurate tracing of each “when” condition for
the cells. This is time-consuming, but the key is to be able to
identify a critical number of cells that will benefit most from such
detailed cycle-based evaluation.
power analysis flow should be able to consume these different types of
activity information and apply them based on design knowledge to
estimate the power at an early stage in the design.