Editor’s note: In part one of this two-part article, the author reviews the history and basic operating principles of ferroelectric RAM (FRAM). Part two will cover design specifics, including thorough discussion of the requirements for the ferroelectric capacitors that form the basis of FRAM.
It was an amazing moment that night in Albuquerque in May of 1987. Richard Womack and I, both at Krysalis Corp., were huddled over a brand new MOSAID memory tester pushing buttons trying to get the display to change. The tester was showing a checkerboard pattern instead of the blank screen it should have had as we set up the tester prior to dropping probes on the very first FRAM fabricated by Krysalis. It was all so very confusing. The tester simply would not respond to our ministrations. No matter what we did, the display kept showing the same write/read checkerboard pattern. We finally realized that the probes were already down on the die and that the memory actually was working after all!
That DUT was the first die on the first wafer on the first lot of the Krysalis 512ECD, and it was 100% functional. Or at least it appeared to be. In reality, it was only 50% functional because we had missed a ground strap for every other word line in the layout. Only half of the 64 bytes were being written and read. A quick change to the metal mask took care of that oversight. Nevertheless, it was an incredible achievement by the technical team at Krysalis, having received venture funding only 18 months prior. Sheffield Eaton at Ramtron followed soon after with his own ferroelectric memory and the race was on.
Every memory technology development project should be so easy. Over the next 20 years FRAM developers ran into all kinds of problems unforeseen by our limited understanding of the physics of ferroelectric materials. Many of these technical and product definition problems were of the same nature, if not in some cases exactly the same problem, as those faced today by other promising non-volatile memory technologies under development like magnetoresistive RAM (MRAM), resistive RAM (RRAM), and phase-change memory (PCM). Despite the long bumpy start, ferroelectric-based memories are now in commercial production with solid product lines. With this foundation, it is my firm belief that the robust nature of the ferroelectric materials underlying FRAMs will allow the rapid creation of new and useful products. In the article below, I will strive to provide a foundation for understanding both the FRAM IC and the underlying ferroelectric materials technology.
Ferroelectricity and FeRAMs There exist families of special dielectric materials with non-linear properties that impart memory to capacitors. These materials are referred to as ferroelectric, meaning they have permanent internal polarization that may be re-oriented by an external electric field. Such a capacitor will exhibit no voltage even though the charges on its plates are not balanced. The physics are simple: 1) Extra charge on the plates cancels the remanent electric field inside the ferroelectric material so that 2) there is no net unbalanced electric field and thus 3) no force to equalize the extra charge between the plates across a short circuit. However, apply an external voltage to the capacitor and the remanent polarization will switch directions, forcing a rebalance of the charges on the plates and creating a dynamic event that can be recorded by external circuitry.
Embedding ferroelectric capacitors into an integrated circuit results in FRAM. FRAM operates internally like DRAM but has the high speed of SRAM plus the non-volatility of flash memory. It is truly a universal memory. When the first successful circuits were built in the 1980s, it was thought that their universal function would allow them to take over all memory functions in digital computers, replacing DRAM, SRAM, and EEPROM. Alas, to the chagrin of the inventors dreaming of fortunes (including this author), that revolution did not happen.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.