Blake cited the example of a DDR 3 memory controller embedded on
Speedster 22iHD1000. “Closing the timing on DDR 3
memory is one of the hardest things," Blake said. "Now that this is embedded as a
cell-based logic on the FPGA, designers need not worry about spending
time on plumbing.”
While area and power savings in the Achronix
FPGA may be clear when compared to the general-purpose FPGAs, true
competitors for Speedster 22iHD1000 are more likely to be ASIC or custom
chips designed for networking and telecommunication equipment. Because
it’s designed as an ideal FPGA for connectivity for high-bandwidth
applications, Achronix will need to pick its spots when pitching Speedster
In certain applications, ASICs could be smaller and
run at less power, compared to Speedster 22iHD1000, Blake acknowledged. But, he said, “They offer no flexibility when it comes to adding new features or
customization.” In the end, he said, this would offer OEMs little
advantage in time and cost.
Breaking the FPGA market into three
categories–low-, mid- and high-end--Blake noted that Achronix FPGAs
are for the high-end market with special focus on high-bandwidth
applications. They include: 200 gigabit line card, systems for the test
space, and high-performance computing area.
Achronix offers a
development kit for the Speedster 22i HD1000, including a PCI Express
form-factor, HD1000 development board, Achronix CAD environment (ACE)
software, programming pod and power supply. The kit including ACE
software is immediately available for $13,000.
Asked what caused
the four and half month delay in the Speedster launch, Blake pointed
to the complexity of the most advanced technology FPGA (over 6 billion
transistors) and working with a new supplier. Calling the delay “a
normal engineering development process,” Blake stressed, “With the extra
time, we gained back in verification and performance of the chip.”
Achronix claims that the HD1000 is exceeding expectations in initial
device testing time, faster SerDes and lower power.
As transistor size goes deeper & PVT issues dramatically increases, asynchronous design techniques become more and more appealing.
Intel knows that, and not only shows its interest throughout the special relation with Achronix.
Few years ago, Intel acquired Fulcrum Micro, maybe the first company that succesfully introduced in the market an asynchronous logic based device.
But the really interesting point is that Achronix doesn't talk about its wonderful asynchronous architecture anymore... what's all this recent secrecy about? What are Intel real intentions with Achronix??
Anytime new chip is released and all the focus is marketing technology “22nm”, "finfet",etc. versus what the chip is delivering (i.e. chip power / chip performance etc. ) highlights there is a problem.
Physical demand for chip is weak. Product level specs are not that competitive with FPGA/ASIC and Acronix marking is pushing risking IP model versus selling chips.
that is the real story
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.