LONDON – Metal-oxide resistive RAM has reached close to the mainstream for array size with a two-layer, 32-Gbit nonvolatile memory prototype implemented by engineers from SanDisk Corp. and Toshiba Corp. in a 24-nm manufacturing process. Engineers from the two companies presented the dual-layered memory at the International Solid-State Circuits Conference (ISSCC).
Resistive RAMs of various types are being developed by a most of the major memory companies and a number of startups as potential replacements for NAND flash at geometries below 20-nm due to their superior scalability. It is expected by many industry observers that ReRAM will be introduced commercially in a vertically-stacked format to take over when vertically-stacked NAND flash runs out of steam. The SanDisk-Toshiba paper therefore offers an important transition to stacked memory structures.
As well as scalability ReRAM is expected to offer fast access, higher read-write endurance and higher reliability than NAND flash. However, the physics behind resistive RAM in various metal-oxide and other forms is still not completely understood.
The ISSCC paper did not reveal which metal-oxide regime SanDisk/Toshiba is using but reported a bit cell planar size of 24-nm by 24-nm and a total die area of 130.7 square millimeters. The I/O interface is NAND-compatible and the read latency is 40 microseconds and the write latency is 230 microseconds.
The 32-Gbit memory is arranged as two stacked layers of 16-Gbit. A scanning transmission electron microscope (STEM) cross-section shows the stack made up of word line 1, device, bit line, device, word line 2. (See paper 12.1 from ISSCC 2013 proceedings: A 130.7 mm2 two-layer 32-Gbit ReRAM memory device in 24-nm technology by Tz-Yi Liu and Tian Hong Yanet al.).
As well as providing two layers of memory array to improve memory density the two-terminal cell with diode selector is stacked above the supporting circuitry. In this work not only are word and bit lines placed under/over the bit cell but also the array control circuit, sense amplifiers, page buffer, and voltage regulator drivers are placed below the memory array.
You said "See paper 12.1 from ISSCC 2013 proceedings: A 130.7 mm2 two-layer 32-Gbit ReRAM memory device in 24-nm technology by Tz-Yi Liu and Tian Hong Yan et al." I'd love to see it - can you point a link to a copy?
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