In addition to the switching current, another important performance characteristic of MTJ bits is their retention time (i.e. nonvolatility), which is determined by the energy barrier Eb between the two magnetic states of the free layer. The larger the value of Eb, the more difficult it is for thermal fluctuations to overcome this barrier to induce false switching events; as a result, retention time increases. Typical values of Eb for 10 years retention in a 1-Mbit array are approximately 60 kT, but the required Eb values may be larger depending on array size and operating conditions.
As mentioned before, large currents required to switch STT-MRAM bits require fairly large transistors to drive them, limiting the memory density. This is in particular a problem for high-speed writing (less than 10 ns), since the switching current of STT-MRAM increases when the write pulse width is reduced. Reduction of the switching current, however, has to be performed at a constant retention time, and hence the real device-level scalability criterion for STT-MRAM is to reduce the ratio Ic/Eb. The smaller this ratio, the smaller the access transistor width can be made for a given technology node and retention time, hence improving the scalability of STT-MRAM. Interestingly, however, for STT-based switching of perpendicularly-magnetized MTJs, the ratio Ic/Eb is largely set by fundamental physical constants and material parameters with a limited tuning range (in particular by magnetic damping). This means that scaling with a constant-Eb rule (i.e. keeping the retention time constant) requires switching currents to remain nearly constant across technology nodes for STT-MRAM. That is unfavorable in terms of scaling as it does not allow for a significant scaling of the transistor width.
The value of Ic/Eb, when combined with the current drive capability of transistors at a given technology node, determines the bit density and hence the application space and cost per bit of STT-MRAM. Current Ic/Eb values of approximately 0.5 µA/kT or higher impose access transistor sizes that are larger than the minimum size approximately at the 32-nm node and below (see figure 4), resulting in a penalty in terms of cell size and bit density. Achieving scalability to below 10 nm, which enables DRAM-like cell sizes of approximately 6F2 at F less than 10 nm, is estimated to require a much smaller scaling parameter of Ic/Eb < 0.1 µA/kT for STT-MRAM. This requires significant advancements in material engineering, especially in the magnetic free layer design.
In order to provide for an improved scaling scenario, as well as to reduce the energy dissipation associated with the current-induced write mechanism, one can use non-STT write mechanisms for magnetic memory bits that can replace or complement the STT-based approach used in today’s MTJs. In the following we describe voltage-controlled (i.e. electric-field-controlled) magnetic tunnel junctions, or VMTJs as candidates for this type of beyond-STT magnetoelectric RAM (MeRAM) and present recent experimental results.
Figure 4: Effect of switching current (Ic/Eb ratio) on the scalability of access transistor size in STT-MRAM. Scaling is significantly improved by dramatic reduction of the switching current, such as through the adoption of a voltage-based write mechanism.