Breaking News
Design How-To

Overcoming the embedded CPU performance wall

3/7/2013 04:40 PM EST
1 Comment
NO RATINGS
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Or_Bach
User Rank
Rookie
re: Overcoming the embedded CPU performance wall
Or_Bach   3/8/2013 11:07:16 PM
NO RATINGS
The statement "Using 3-D transistors instead of the previous planar structure transistors, pipeline stages can be vertically stacked on top of each other, effectively reducing the distance between blocks and eliminating wire delay effects." is correct in respect to the advantage associated with monolithic 3D technology, but it has nothing to do with the Fin-FET transistor also known as 3-D transistor. You can find more information in "MonolithIC3D.com" web site

Flash Poll
Radio
LATEST ARCHIVED BROADCAST
EE Times editor Junko Yoshida grills two executives --Rick Walker, senior product marketing manager for IoT and home automation for CSR, and Jim Reich, CTO and co-founder at Palatehome.
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed