Report rate and sleep mode work together to define how the capacitive touch sensors are sampled, as shown in Figure 2. Report rate defines how often the sensors are sampled by the A-to-D converter. When a sensor is sampled, the capacitive sensing controller is in active mode. When a sensor is not being sampled, the controller can be put into sleep mode. In sleep mode, the controller powers down all internal blocks and peripherals. This mode is supported by most of the capacitive sensing controllers on the market.
Figure 2: Sensor sampling with sleep mode
Click on image to enlarge
Selecting a low report rate and a longer sleep time are the keys to reducing the average power consumption. Report rate and sleep mode directly affect the capacitive sensing controller’s average current consumption, as defined in Equation 1.
Equation 1: Average current calculation
IActive = Current consumed by the controller when it is sampling a sensor
TActive = Time it takes the controller to sample all of the sensors
ISleep = Current consumed by the controller when it is in sleep mode
TSleep = Amount of time the controller remains in sleep mode
As a general rule of thumb, a human finger cannot touch a button faster than 150 ms. Typical A-to-D conversion times range from 200—6000 µs. This means that several A-to-D conversions can be performed during the 150 ms a sensor is being touched. Optimize the report rate for your specific A-to-D conversion time.
Reducing CP helps to reduce TActive because the controller can use a lower A-to-D converter resolution. Selecting a capacitive sensing controller with lower active current reduces IActive. Keep in mind that sleep mode current has a minimal impact on the average current.
Hi, Article details about the management of activities to enhance battery life but didn't discuss the details of the measurement of capacitance which the most critical part of this technology. Measurement of C using A/D is not straight forward & needs a lot of consideration to avoid false or no key detection.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.