This design article comes from the book Practical Applications in Digital Signal Processing by Richard Newbold and will be presented in several parts. The book is published by Prentice Hall and is a massive 1152 pages. An outline of the book including preface and chapter descriptions is provided here. Available in both print and eBook formats. See the Prentice Hall site for more information or from Amazon.
Part 1 of this chapter appeared here and examined digital data locked design, elastic stores, error signals and error voltages, clock frequency synthesis and expected digital data locked operational characteristics.
The next part of the chapter deals with a mathematical evaluation of the steady state and transient behaviors including a couple of methods to calculate the constant k. Because of the number of formulas involved and the limited formatting capabilities, the section is provided as a pdf.
11.4 Data locked loop bit-level simulation
Equation 11.16, which is repeated here for clarity, says that we should expect the DLL transient bit clock frequency response to take on the shape of an exponential in response to a step in the input bit clock frequency.
We will see in this section that this is true.
11.4.1 Description of the software simulator screen
Before we begin, let’s spend some time getting familiar with the author’s DLL bit-level software simulator, which runs in Microsoft Windows. The parameters for each simulation are entered via the dialog box illustrated in Figure 11.14.
The dialog box contains three control groups:
- MDAC parameters group
- Reference voltage VREF. This allows the user to assign values for the MDAC input reference voltage. In our design, this is set to 3.0 volts.
- Resolution. This allows the user to assign value for B, which is the width in bits of the digital error signal eD. It also sets the size of the elastic store memory to 2B. In our design, this is set to 10 bits.
- VCXO parameters group (note there are several parameters here but only the two we are interested in are listed)
- Center frequency FS. This is the center frequency of the VCXO. In our design, the value of this parameter is 1.544 MHz.
- Frequency deviation FD. This allows the user to assign the pull range of the VCXO. In our design, the value of this parameter is ±100 ppm.
- Input tributary parameters group
- Center frequency FI. This is the center frequency of the input tributary bit clock and is set to 1.544 MHz.
- Center frequency variance. This allows the user to assign a value to the variance of the ideal center frequency. In our design, this value is set to 0 Hz.
- Center frequency max variance. This allows the user to specify the maximum tributary frequency variance. In our design, this value is ±50 ppm.
Figure 11.15 illustrates a blank simulator plot screen. On the left of the screen are two vertical axes. The one on the far left represents the range of the VCXO synthesized frequency with limits at FS ± Max ppm. The VCXO center frequency on this vertical axis is labeled FS. In this simulation, FS = 1.544 MHz. The horizontal time axis passes through this center frequency point.
Figure 11.14 Software simulation parameters dialog box
Figure 11.15 Software simulation plot screen
The second vertical axis represents the range of the VCXO error voltage VO with limits of 0 to VO volts. In our design, the max value for error voltage is 3 volts. The horizontal time axis passes through the midpoint of this range at VO / 2 = 1.5 volts . For our design, the maximum value of fS that we can plot is 1.544 MHz + 50 ppm or 1.544 MHz + 77.2 Hz, and the minimum value we can plot is 1.544 MHz - 50 ppm or 1.544 MHz - 77.2 Hz. The voltage range extends from 0 to 3 volts. In our 10-bit design, the maximum value of VO we can plot is 2.25 volts and the minimum is 0.75 volts.
The plot of the DLL transient response is read left to right on the screen, just like any normal graph. However, the plot data is entered on the right-hand side of the plot window and is scrolled to the left as additional plot data are entered. The plot continues to scroll across the plot window from right to left until the user stops the simulation. For this reason, a snapshot of a plot in progress may show the plot being skewed to the right of the vertical axis, but this is only because the plot has been stopped and has not completely scrolled across the full length of the plot window. The reader should visualize the point corresponding to the time t = 0 as scrolling from the right side of the plot to the left side and beyond. The points on the left of the plot correspond to the oldest in time and the points on the right of the plot correspond to the newest in time.
The minor and major tick marks on the time axis are scrolled from right to left along with the plot data. The distance between minor tick marks on the time axis is the equivalent of a million input bit clock periods. The distance between major tick marks on the time axis is the equivalent of 10 million input bit clock periods.
On the right of the plot screen are several variables that are constantly monitored and updated as the plot data is computed and as the plot scrolls across the plot window. These variables represent critical DLL circuit parameters. They are continuously being computed and displayed in real time as the data are plotted. This allows the user to view the behavior of the parameters with respect to time. These variables are defined from top to bot-tom in Table 11.5.
The simulation plots illustrate the synthesized frequency and the error voltage of the DLL over time in response to a step in the input bit clock frequency. In order to distinguish the two on a black and white plot, the synthesized frequency is shown as a thick line and the error voltage is shown as a thin line. With that said, let’s take a look at a few simulations so we can graphically see the loop response in action. It is important to note that the software simulator does not plot data produced by the transient response equations we derived in the previous section. The simulator is a bit-level simulator that simulates the actual hardware architecture and plots the response of the DLL hardware circuit over time. We will expect to see the simulation results agree with the results independently obtained from our previously derived equations.
Table 11.5 DLL Simulator Parameter Definitions