The ubiquitous and ever increasing presence of microprocessors in many system-on-chip (SoC) designs has led to a significant proliferation of embedded memories. These chips can have more than 100 embedded memory instances, including ROMs, RAMs and register files that consume up to half the die area. Some of the most timing-critical paths might start, end, or pass through some of these memory instances. Thus, the models for these memory elements must accurately account for process, voltage, timing and power variability to enable truthful chip verification. Memory characterization is the process of abstracting a memory design to create an accurate timing and power model most commonly used by downstream implementation and signoff flows. Ad-hoc approaches to memory characterization do not accurately model the data required for faithful SoC signoff, delaying tapeout and increasing the total cost of the design.
Memory characterization often requires hundreds of SPICE simulations. The number of memory instances per chip and the need to support a wide range of process, voltage and temperature corners (PVTs) make these simulations a daunting task. Also, the growing size of memory instances and sensitivity to process variation add more dimensions to an already challenging undertaking. Further, the need to create library variants for high-speed, low-power and high-density processes makes it imperative to automate the memory characterization flow.
This article considers several existing approaches to memory characterization and discusses their benefits and challenges. The article also proposes a new dynamic partitioning methodology that addresses the limitations of existing approaches and enables the capacity and throughput requirements for characterization of multimillion-bit memory cells.
Overview of memory characterization methodologies Broadly speaking, there are two main methodologies for memory characterization. The first one is to characterize memory compiler-generated models and the second is to characterize individual memory instances. Further, there is an assortment of approaches for instance-based characterization, including dynamic simulation, transistor-level static timing analysis and ad-hoc divide and conquer.
Memory compilers construct memory instances by abutted placement of pre-designed leaf cells (e.g., bit-columns, word and bit line drivers, column decoders, multiplexers and sense amplifiers, etc.) and routing cells where direct connection is not feasible. The compiler also generates a power ring, defines power pin locations and creates various electrical views, netlists and any additional files required for downstream verification and integration.
Memory compilers do not explicitly characterize the generated cells but instead create models by fitting timing data to polynomial equations whose coefficients are derived from characterizing a small sample of memory instances. This approach enables memory compilers to generate hundreds or thousands of unique memory instances, differing in address size, data width, column/row density and performance. However, the model accuracy of this approach is poor.
To safeguard against chip failure due to inaccurate models, the memory compiler adds margins. These can lead to more timing closure iterations, increased power and larger chip area, however. In addition, the fitting approach doesn’t work well for the advanced current-based models: effective current source model (ECSM) and composite current source (CCS), which are commonly used for timing, power and noise at 40 nm and below.
To overcome the inaccuracies of compiler-generated models, design teams resort to instance-specific characterization over a range of PVTs. This is a much more time-consuming process that yields more accurate results. However, often due to limitations in the characterization approach and available resources, the accuracy improvement is not as much as it could be, while the cost is high.
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