One method for instance-based memory characterization is to treat the entire memory as a single black box and characterize the whole instance using a FastSPICE simulator. The advantage of this method is that it enables the creation of accurate power and leakage models that truly represent the activity of the entire memory block. It can also be distributed across a number of machines to speed-up simulation time. Unfortunately, this approach is not without disadvantages—namely, a FastSPICE simulator trades off accuracy for performance. Further, the black box approach still requires users to identify probe points for characterizing timing constraints. For a custom memory, the characterization engineer can get this information from the memory designer, but this information is not available from memory compilers. Finally, this method doesn’t work well for generating some of the newer model formats such as noise models, and cannot be scaled to generate process variation models needed for statistical static timing analysis (SSTA).
A second approach for memory characterization is using transistor-level static timing analysis (STA) techniques that utilize delay calculators to estimate the delay of sub-circuits within the memory block to identify the slowest paths. The advantages of this method are fast turn-around time and the fact that it does not require vectors to perform timing analysis. However, STA techniques suffer from identifying false timing violations that require further analysis with SPICE/FastSPICE simulators to determine if these are of real concern.
The STA approach is also impaired by pattern matching, which needs to be constantly updated as new circuit structures are introduced across different designs and new revisions. The existence of analog structures like sense amps in the critical paths of the clock-to-output data makes the setup of the STA approach more demanding. Further, the underlying usage of transistor-level delay calculators, which are process- and technology-dependent, undermines its claimed SPICE accuracy, as it assumes that delays from active elements and the RC parasitic elements can be separated. However, this is no longer the case due to the presence of parasitic elements in between finger devices, which are a typical result of extraction on memory structures in advanced process nodes.
Finally, a static delay calculator is in general severely compromised—either in terms of runtime, accuracy, or both—by the presence of large transistor channel-connected regions. Therefore, a memory array is arguably the worst application for a static timing analysis. This is especially true in the presence of power-gating methodologies, which are commonly adopted for any memory design at 40 nm and below.
Another approach to memory characterization is to statically divide the memory into a set of critical paths, characterizing each of these paths using an accurate SPICE simulator and then integrating the electrical data from each of these components back into a complete memory model. The advantage of this approach is the accuracy gained using SPICE simulations with silicon-calibrated models. The simulations can also be distributed across a computer network with each critical path being simulated independently.
The disadvantage is that for advanced memories, in which there is significant coupling or a virtual power supply network, the circuitry making up the critical path grows too large for a SPICE simulator to complete in a reasonable amount of time. In addition, SSTA model generation, especially for mismatch parameters, becomes prohibitively expensive in terms of turnaround time with such a large circuit. Further, the static-divide approach is challenged by the need to correctly identify the clock circuitry, memory elements and tracing of critical paths through analog circuitry such as sense amps for different memory architectures with varying circuit design styles.
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