SANTA CLARA, Calif. – Transistors may or may not keep getting cheaper, but in either case, the semiconductor industry still has plenty of headroom for growth, said Aart de Geus.
The co-chief executive officer of Synopsys is bullish on the industry’s abilities to master FinFETs and double patterning, but cold on 3-D chip stacking. In a keynote and press roundtable at an annual users group meeting here de Geus also vowed to make the Verdi debugger recently acquired with Springsoft the centerpiece of an updated verification offering and to migrate the Eve verification system to run on graphics processors.
“Moore’s Law has become irrelevant compared to the impact of new applications,” de Geus told several hundred engineers here. “Even if transistors do not become that much cheaper the demand for more capabilities will continue at breakneck speed and the economics will be there."
It costs $5-$7 billion to build a 14-nm fab today, and any chip coming out of it will have to comply with thousands of design rules, he noted. The need to use double patterning lithography and move to FinFET transistors is the next layer of that complexity, de Geus said. Nevertheless, he expressed optimism in the face of those challenges.
“For the first time, we can predict we can get to single-digit nanometer chip sizes,” he said in his keynote. “A number of chips are already designed with double patterning with our place and route tools [and] the number of companies committing to FinFETs has grown substantially,” he said.
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Tapeouts on advanced nodes continue despite rising complexity, de Geus said.
“The race is very much on [among Globalfoundries, Samsung and TSMC] for who will have what [FinFET] capabilities when,” he said at the press roundtable.
For the coming “20-nm planar node the attraction is not that hot--there are all the cost increases and very few power improvements,” he said, frankly. He also noted the 14-nm FinFETs will arrive in a process that uses 20-22 nm interconnects, but “once FinFETs are at reasonable cost, a number of people will be full bore on it” and the current 28-nm node “will be big,” he told press.
De Geus is less bullish on 3-D stacks. He called them effective “for some areas that’s like memories together with sensors, but in general they are difficult and expensive so if we can put more on chip we will,” he said.
Chips built in the latest nodes must obey thousands of design rules, de Geus said.
I think that the answer is both yes and no. Initially, they are more expensive but provide increased density/speed or lower power. As the technology matures they will trend towards cheaper. I think the greatest challenge to the designers and tool users is and will be addressing the complexity of the design and the verification effort needed. If Synopsys can provide the tools to help with the complexity and verification then they will be successful.