LONDON – Programmable logic company Tabula Inc. has announced support for 100-Gbit per second Ethernet communications based on a forthcoming ABAX2 series of devices, which are being made by Intel using its 22-nm FinFET manufacturing process.
Engineering samples of the first chip in the series, the ABAX2P1, will be available in Q3, Tabula said. EDA support, packet processing reference designs and related soft IP blocks are already available to allow 100G design work to start.
The ABAX2P1 – which ten-year old Tabula (Santa Clara, Calif.) calls a PLD rather than an FPGA – is a 12-fold "Spacetime" device which means that it can support 12 different configurations in its SRAM look-up tables and cycle through them as a way of supporting up to 12 times more logic than a conventional FPGA architecture would on the same fabric. It also includes additional RAM, logic and interconnect capabilities alongside hard IP blocks to customize the device for packet processing applications, Tabula said.
The chip supports 2-GHz clock frequency throughput through every component of the chip and provides 23.3-Mbytes of 12-port or 24-port on-chip memory providing for up to 13.8-Tbytes per second of throughput. The FPGA fabric includes 570,000 LUTs and 70,000 logic carry blocks, although it is not clear whether these figures are before or after the 12-fold time-slicing. There are multiple DDR3 memory controllers and 100G Ethernet media access controllers (MACs) and the chip includes multiple instances of 10G/40G/100G forward error correction blocks.
The overall combination will support processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12 times 10G into 100G bridge.
To design with the ABAX2P1 Tabula provides the Stylus compiler software which maps standard RTL to the ABAX device taking into account the time-sliced nature of the FPGA fabric. It includes sequential timing, router aware placement, and automatic co-optimization of performance and density.
A packet processing reference design suite includes reference designs for 12 by 10G-to-100G bridge, a 4 by 100G switch, and a ternary search engine. Tabula is also able to provide soft IP cores including: a 600Gbps packet classifier, a 100Gbps 64-bit CRC generator, and a 1.3-Tbps L2 packet parser.
The initial set of packet processing solutions is already available in Stylus.
"The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs," said Dennis Segers, CEO of Tabula, in a statement. "With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway."
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