LAKE TAHOE, Nev.—Three-dimensional integration was the focus on the kickoff day for the annual International Symposium on Physical Systems (ISPD), where semiconductor designers worldwide show-off their next-generation aspirations for the physical design of future chips.
Keynoting the 3-D track was veteran chip architect Liam Madden, vice president of FPGA development at Xilinx Inc. (San Jose, Calif.) who claimed that chip designers can have their 3-D cake and eat it, too.
"For many years, designers kept digital-logic, -memory and analog functions on separate chips—each taking advantage of different process technologies," said Madden. "On the other side are system-on-chip [SoC] solutions, which integrate all three functions on the same die. However now there is a third alternative that takes advantage of both worlds—namely 3-D stacking."
Since the beginning of semiconductor development, designers have stuck with Moore's Law, integrating more and more functionality onto their chips. Madden believes that Fred Weber, former chief technology officer at Advanced Micro Devices Inc., may have said it best when he said: "Integrate or be integrated."
For years, this knee-jerk reaction drove processor designers to integrate more-and-more peripheral functions out of fear that other companies would beat them to the punch and become so successful that they eventually acquire them. Eventually, the success of the monolithic integration approach prompted designers to begin integrating memory and analog functions onto processors, too, resulting it SoCs.
Xilinx's Virtex-H580T combines two FPGAs with a high-speed transceiver and the necessary analog functions on in a single package by virtue of a 3-D silicon interposer.
Madden proposes using silicon interposers to integrate separate dies for processing, memory and analog into 3-D stacks, thus combining the best of both worlds—increased density that to programmers looks exactly like an SoC, but by retaining the ability to using different processes technologies each optimized for their assigned task.
Xilinx's first implementation was its homogeneous Virtex-7 H580T, which combined four Xilinx FPGAs into a single package, integrated by a silicon interposer built by Taiwan Semiconductor Manufacturing Co. (TSMC). However, its latest 3-D chip stack, the Virtex-7 H580T, is heterogeneous—combining two FPGAs with the a 2.8-Gbit per second transceiver and , there by implementing a serdes that is the only single-chip solution for 400Gbit per second line cards.
For the future, Xilinx plans to continue integrating heterogeneous die with silicon interposers, in order to combine the best of both worlds, with its next slated offering the Virtex-7 H870T which uses a silicon interposer to integrate three FPGA die with two 28-Gbit per second transceivers and the necessary analog functions in the same package.
Others sessions in the ISPD 3-D integration track included Taiwan's Industrial Technology Research Institute scientist, Pei-Wen Luo, presenting benchmarking methods for 3-D power delivery networks. Dresden University of Technology researcher Robert Fischbach presented 3-D floor-planning techniques using reusable rectilinear IP blocks. And Universitat Politecnica de Catalunya researcher Jordi Cortadella presented physical-aware system-level design methods for creating 3-D tiled hierarchical chip multiprocessors. Related stories:
From your desciption it appears that strictly speaking the new Xilix module ( just like their first one ) is NOT a 3-d but 2.5d ( i,e. no pesky TSVs in active dies, only in Si interposers and no stacking of active dies ).
Can you comment please.