LONDON – Moortec Semiconductor Ltd. (Plymouth, England), a provider of mixed-signal IC design services and IP whose customers include AMD, Broadcom, Intel and Imagination amongst others, is seeking a partner and first customer for a technology it calls receiver efficient mobile communications (REMC).
REMC is an algorithmic enhancement to cellular baseband reception that the company claims provides performance and power consumption improvements over conventional decoders in the receive chain. The software does not deviate from the established 3GPP standards and the benefits can be obtained across HSPA, HSPA+, 3G (WCMDA and TDSCDMA) and 4G (LTE TDD and FDD) transmissions, the company claims.
The benefits are less lost packets of data, improved reception at cell edges and more power efficient data transmission, the company claims. In addition the change only needs to be applied on the receive side of the transmission so benefits can come from changes only at one side of the wireless connection – changes can be additive, say to handsets, and do not have to be system-wide.
Moortec also claims that REMC performance is better than conventional MIMO type receivers under all conditions. A first prototype has been written in C making it easy to integrate with existing receiver architectures, the company said.
Stephen Crosher, CEO of Moortec, said REMC is essentially an improved receiver implementation that would reduce the number of retransmissions required for error-free packet reception, but declined to provide technical details of the algorithmic approach.
Crosher said the need for retransmission of packets in cellular communications is already an issue for mobile phone service providers and users, although users are not usually aware of how many packets are resent. This is going to become worse as the volumes of data transmitted increase, said Crosher.
Click on image to enlarge.
One of the slides from a five-minute elevator pitch for REMC. Source: Moortec Semiconductor.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.