LAKE TAHOE, Nev. — Design contests at conferences often pit engineering teams against one another, but rarely do they advance the state-of-the-art. An exception are the contests run by the Association of Computing Machinery (ACM) at its International Symposium on Physical Systems (ISPD) here. Each year engineering teams from around the world compete to advance the state-of-the-art, which in past years has focused on metrics such as faster speeds. In this age of slow clock-speed growth, however, the annual ISPD contest has turned to smarter algorithms for lower-power operation.
In this year's Discrete Cell Sizing Contest, 25 engineering teams from eight different countries competed to optimize gate-size and threshold voltages for a given circuit to achieve the lowest possible operating power that still satisfied performance constraints.
"Cell size is usually related to its power consumption--the smaller the size the lower the power," said Intel research engineer, Mustafa Ozdal, who organized the contest this year with help from Intel, Cadence and Synopsys. "So to simplify the evaluation of entries, we decided to compare leakage current this year."
Contests historically run in pairs, with the second year's version raising the bar in evaluation criteria, and the 2013 contest was no exception. This year contestants were provided with the same circuit netlist as for last year's contest--but with an improved benchmark suite and more realistic timing model. Included was a standard cell library with a set of benchmarks for a Verilog netlist, interconnection parasitics and timing constraints. Each engineering team crafted algorithms to compute discrete size and threshold voltage for each cell in the netlist. Judging was based on rewarding the lowest total leakage current that satisfied the provided timing constraints. Synopsis' PrimeTime was used to accurately identify the timing violations of each contestant's design.
|Comparisons of leakage current results for the top three contest entries in the Discrete Cell Sizing Contest normalized to the winning Team South Brazil (red) compared to Team Trident (green) and Team GoodTime (blue) on the nine primary evaluations.|
Click on image to enlarge.
Of the original 25 teams, only nine complete submissions made it to the final evaluation phase. Taking first place was Team South Brazil (Universidade Federal do Rio Grande do Sul and Universidade Federal de Santa Catarina, whose members included Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo Johann, Ricardo Reis, Vinicius Livramento, Chrystian Guth and Renan Oliveira Netto and professor José Luís Güntzel). Second place when to Team Trident (University of Michigan whose members included Seokhyeong Kang, Pankit Thapar, Hyein Lee, Benjamin VanderSloot and professor Igor Markov). And third place went to Team GoodTime (Keio University and National Chiao- Tung University) whose members included Li-Chung Hsu and Simon Yi-Hung Chen.
Separately, the "Best Paper" award this year went to IBM's Hua Xiang, Minsik Cho, Haoxing Ren, Matthew Ziegler and Ruchir Puri for their paper Network Flow Based Datapath Bit Slicing
, which presented a smarter algorithm--than the current use of template-, location- and name-matching--for automatic datapath-aware latch-bank planning for bit slices.