In recent years, applications such as digital cameras, MP3 players and SSDs have been enabled by the development of increasingly higher-density NAND Flash memory. To scale the flash memory array below 20 nm, improved management of effects like floating-gate-to-floating-gate (FG-FG) interference and distribution shifts due to cycling, retention, and quick charge loss are essential. These effects deteriorate the read-window budget (RWB) needed to place the eight distributions associated with the 3 bit-per-cell device. Process and design changes to maintain the RWB needed for a reliable product are required.
Last year for the first time, we demonstrated a new planar cell technology [1,2] that allows scaling of NAND devices below 20 nm in both word-line (WL) and bit-line (BL) directions. In planar cell technology, floating gates (FGs) have a significantly
lower aspect ratio (A.R) compared to conventional wrap-around FG cells
in which A.R becomes better than 10 for both WL and BL directions once
devices are scaled below 20 nm. Therefore, the planar FG removes number
of physical and electrical scaling constraints.
This year at the IEEE International Solid-State Circuits Conference (ISSCC 2013), we presented the first 3 bit-per-cell 128-Gb device using the planar-cell technology, clearing the path for further cost reduction . Here, we describe key improvements and innovations that are needed to produce the smallest 128-Gb, 3 bit-per-cell product.
We based the sensing scheme on a ramping technique that allows the detection of hard and soft states in a single operation. The data cache structure is designed to efficiently manage features that optimize the RWB, including pre- and post-compensation to mitigate floating gate to floating gate (FG-FG) interference. The design also includes read algorithms to minimize the bit-error rate by tracking eventual distribution shifts due to cycling, retention, and charge loss. The I/O interface allows ONFI 2/3 protocols for data-in/out with a 6-ns cycle. Array access in the 3 bit-per-cell configuration allows a sustained write throughput of 4 MB/s and a 100 MB/s read speed.
The cross-section of the planar 20-nm cell is shown in figure 1. Key features of the planar-cell technology include thin-poly floating gates to reduce cell-to-cell interference, a metal control gate, air-gap isolation for both cell gates and metal BLs to reduce coupling capacitance, and a high-k inter-gate dielectric.
Figure 1: Planar NAND cell cross-section
As technology nodes scale down, the
interference between adjacent memory cells increases significantly for
WRAP cells. This trend will accelerate further beyond 25 nm; the
planar cell slows this trend (see figure 2).
Figure 2: Curves compare FG-FG interference for WRAP cells
with air gap (red) and without air gap (blue), compared to
planar cell (green).
The 128-Gb, 3-bit-per-cell NAND flash memory in the 20-nm technology node is organized into two planes (see figure 3). Each block consists of a NAND string having 128 physical WLs corresponding to 768 pages (lower, middle, and upper page). Each page is 8-kB long and is organized into even/odd pairs with a single sense amplifier for each pair of BLs.
Figure 3: Die picture shows 20-nm, 128-Gb, 3-bit-per-cell NAND flash