The read mechanism is based on a ramped WL sensing circuit and multi-latch page buffers . The ramped WL sensing technique consists of a counter having its output WLDAC connected to a DAC circuit generating a ramped WL waveform during read operation. At every step of the WL ramp, a sensing operation is performed. Only when the WL voltage is greater than cell Vt, the selected cell is turned on and PBDAC digital value is loaded into a corresponding pagebuffer.
The voltage for the selected WL during the read and verify operations is generated by a dedicated analog sub-system (see figure 4), designed to shape a digitally controlled voltage ramp. This hardware allows control of the slope of the voltage ramp and the ability to perform temperature compensation. A dedicated resistor ladder is used to generate the voltage levels of the voltage ramp between the initial and final values. The controller performs the ramp generation through this sub-system, driving the ramp generation register (REGISTER_0) with an appropriate counter.
Click image to enlarge
Figure 4: Dedicated analog subsystem generates the voltage
for the selected write line (WL) during the read and verify operations. The analog subsystem resides in the periphery support circuitry below the memory array.
Pages are programmed in this order: first the even, then the odd on the same WL, and then higher-order WLs. During the program operation, the even pages can suffer interference due to the subsequent program operation of the odd in the same WL or to the subsequent program operation of the higher-order WLs. New features have been developed to compensate for the FG-FG in both write and read operations. This technique compensates for the FG-FG interference based on an internal algorithm, evaluating the aggression level from adjacent cells and appropriately positioning the target cell. The final distributions achieved are shown in figure 5.
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Figure 5: Plots of error versus the eight threshold voltages
used to store data on a 3-bit-per-cell demonstrate
consistent performance across a statistically meaningful
sample size; the separation of these levels indicate
the available read-window budget.
The corrective read technique is activated by the external controller and is performed internally in the memory. The purpose of this feature is to perform data correction due to FG-FG interference during the read operation after both the victims and the aggressors have been programmed. The corrective read technique detects if the surrounding cells, acting as aggressors, have been programmed and adjusts the read level of the target cell accordingly. The channel calibration technique uses an algorithm executed on the NAND die to detect the read level that minimizes the bit error rate.
As flash memory scaling through traditional means becomes more difficult, the memory community needs to investigate new approaches to allow NAND flash to scale beyond 20-nm processes. Planar-cell technology delivers solid performance and the promise of economical, high-density memory.
 A. Goda, et. al. IEDM 2012, 2.1.1
 S. Barak, “Intel, Micron on sub 20-nm and insatiable thirst for memory,”
 G. Naso, et. al. ISSCC 2013, 12.5
 Sarin et. al., USPTO patent 7,948,802 (2011)
About the author
Ramin Ghodsi is the senior director of design engineering for Micron’s NAND Solutions Group. He has over more than 20 years of experience in semiconductor design and technology. For the last 14 years at Micron, he has served in various senior-level engineering and management positions in flash memory and NAND product development. In his current role, he is responsible for nonvolatile memory design centers in California, Japan, Italy, and China, which design NAND products for Micron and IMFT. Dr. Ghodsi holds a Ph. D and a Bachelor of Engineering degree, with honors, from the University of Queensland, Australia. He has also contributed extensively to the field of semiconductor design, device, and technology through filed patents and refereed journal and conference publications.