LONDON – Processor IP licensor ARM Holdings plc (Cambridge, England) and foundry partner Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) have completed the first tape out of a Cortex-A57 processor on 16-nm FinFET process technology.
The Cortex-A57 is ARM's highest performance processor so far, complies with the ARMv8 instruction set architecture supporting 64-bit addressing and is the "big" processor in a big-little pairing with the Cortex-A53. The processor is set to be part of ARM's attack on the server market but is also expected to find use in mobile and enterprise computing including high-performance computing and tablets.
ARM and TSMC worked together for six months on the implementation from RTL to tape-out using Artisan physical IP from ARM, and memory compilers and EDA technologies from TSMC's design partners. The test chip was implemented using a commercially available tool chain and design services provided by companies associated with ARM and TSMC.
No indication was given of when ARM and TSMC expect to see first silicon of the Cortex-A57 implemented in 16-nm FinFET process, or what sort of performance is expected. A spokesperson for ARM said that Cortex-A57 power-performance-area trade-offs will not be finalized until further in the collaboration. The spokesperson added that TSMC estimates the 16FF process will provide approximately 40 percent more speed for the same total power when compared to the 28HPM CMOS manufacturing process.
As test chip this is first instantiation is not expected to be deployed commercially but is means to calibrate the manufacturing process and particular design choices and to speed up the time to market for licensees of the Cortex-A57 and ARMv8 architecture.
"This achievement demonstrates that the next-generation ARMv8 processor is FinFET-ready for TSMC's advanced technology," said Cliff Hou, TSMC vice president of R&D, in a statement.
A spokesperson for TSMC has told me that they won't be putting out any SEM cross-sections of the 16FF process until ICs made using the process have been sold.
Once that happens third parties can buy some chips, take a saw to a chip and take their own microphotographs. So TSMC may leave it up to those third parties or release some of their own.
"New ARM Architectures for Servers: 64 bit, Virtualization, and Energy Efficiency".
I want to see cross sections.
I want to know Fin height variations within a die and across the wafer.
I don't need some marketing BS
On April 9, ARM talk on "New ARM Architectures for Servers: 64 bit, Virtualization, and Energy Efficiency". Attend event in San Jose or on-line: http://sites.ieee.org/scv-cs/ by IEEE Computer Society Santa Clara Valley
"The test chip was implemented using a commercially available tool chain and design services provided by companies associated with ARM and TSMC."
Did TSMC provide by any chance SEM cross sections?
I am curious about fin height variations for example
what's the shape look like?
Do they look similar to Intel
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.