LONDON – Professor Chenming Hu of the Graduate School at the University of California, Berkeley, has been announced as this year's recipient of the Phil Kaufman award.
The award is given annually by the EDA Consortium (EDAC) and the IEEE Council of EDA (CEDA) and Professor Hu has been recognized for his contributions in device physics, device modeling, and device reliability through BSIM and BERT models that have transformed the semiconductor manufacturing and electronic design automation industries.
Previous winners of the Kaufman award have included Professors Richard Newton and Alberto Sangiovanni-Vincentelli of UCB, Hugo de Man of IMEC, Phil Moorby the inventor of the Verilog design language, Joe Costello a former CEO of Cadence and Aart de Geus long-time CEO and now co-CEO of Synopsys.
More than a decade ago Hu and researchers working with him invented the revolutionary three-dimensional FinFET, a structure that provides a route to achieve size and power reduction for integrated circuits and which has been introduced commercially by Intel. Foundries Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) and Globalfoundries Inc. (Milpitas, Calif.) are planning to introduce their own FinFET manufacturing processes in 2014.
The Kaufman award celebrates Professor Hu's contributions to EDA and in particular the BSIM compact models that used in the design of all types of integrated circuits, spanning logic, memory, analog and RF products. Professor Hu has also made significant contributions in device physics and non-volatile memory.
"Recognizing Chenming Hu the very year in which the entire EDA, IP, and semiconductor industry is unleashing the next decade of IC design through the 16/14-nm FinFET generation is not a coincidence, but illustrates how a great contributor can impact an entire industry," commented Aart de Geus, chairman and co-CEO of Synopsys, and chairman of the award selection committee of the EDA Consortium, in a statement.
Professor Chenming Hu, the TSMC Distinguished Professor of the Graduate School at the University of California, Berkeley, is set to receive the Phil Kaufman Award at the 2013 Design Automation Conference.
Professor Hu received a bachelor degree from National Taiwan University, masters and PhD degrees from UC Berkeley. He served on the faculty of MIT and UC Berkeley as well as the chief technology officer for TSMC, the world's largest semiconductor foundry. In 2001 he founded Celestry Design Technologies Inc., which was acquired by Cadence Design Systems Inc. in 2003. Professor Hu was elected to the US National Academy of Engineering in 1997 and the Chinese Academy of Sciences in 2007. He has received numerous other prestigious awards from learned societies and national and international bodies.
Professor Hu will receive this award at the opening ceremony of the Design Automation Conference, which runs from June 2 to June 6, in Austin, Texas.
Great choice for the award! Amazingly, Dr. Hu also contributed to the development of FD-SOI, which ST and Thomas Skotnicki refined to the very efficient Ultra-Thin Body and Buried Oxide FD-SOI, a Faster, Simpler, and Cooler technology for nano-scale semiconductors.
(Full Disclosure: I work for STMicroelectronics and Thomas Skotnicki is a colleague.)
Even though I never had a chance to work with him. I have read many of his papers and book. including FINFET and latest BSIM book. Well deserved award.
With made in US hat.
We devloped all this in US, going to manufacture from Taiwan...
As Mike pointed out above, Chenming Hu did seminal work on both FinFETs (1999) and FD-SOI (2000) -- both of which, in his original papers, were based on SOI. He recently wrote about why SOI still has important advantages for fully-depleted devices, both planar (FD-SOI) and vertical "FinFET" See his piece at: http://www.advancedsubstratenews.com/2012/04/chenming-hu-soi-can-empower-new-transistors-to-10nm-and-beyond/
For those interested in the history of fully depleted devices, it is important to remember that all these guys really "stand on the shoulders of giants". For what eventually became known as FinFETs, the first reference is probably a Hitachi paper on what they called the "Delta" dating back to 1989: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=74182&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D74182. A steady stream of fully-depleted papers from the worldwide research community followed from there.
The term "FD-SOI" appears to have been coined by JP Colinge in 1998 -- (see http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=669511&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D669511). JPC we went on to do important work on all flavors of fully-depleted fabrication, theory and applications (he received the IEEE Andrew Grove Award last year "For contributions to silicon-on-insulator devices and technology").
In 1983-4 Lim and Fossum in 1983-4 referred to "completely depleted SOI" and even before, Worley in 1980 advanced a "theory of the fully depleted SOS MOS transistor". (My thanks to D. Flandre at UCL, who is also one of those fully-depleted "giants", for pointing all this out to me last year.)
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