Editor’s note: This work was first presented at the 2012 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE. For more information about IEDM 2013 (Washington DC; December 9-11), click here.
We review key properties for commercial ST-MRAM circuits, discuss the challenges to achieving the many performance and scaling goals that are being addressed in current development around the world, recent results in the field, and present first results from a new, fully-functional 64-Mb, DDR3, ST-MRAM circuit.
Spin-torque magnetoresistive random access memory (ST-MRAM) is being developed for a number of purposes: extending MRAM technology to densities beyond those achieved with toggle switching, enabling embedded nonvolatile memory with a small cell size, and as an eventual successor to high-density DRAM with the potential to solve extreme scaling problems.
Figure 1 shows typical memory cells for toggle MRAM, the field-switched technology in production today at Everspin, and ST-MRAM, both with a one magnetic tunnel junction (MTJ) and a pass transistor per cell. In both cells the data is stored in the magnetic state of the MTJ and read back by sensing the corresponding resistance of the MTJ. In toggle MRAM, the free layer magnetization is switched by a magnetic field created by current pulses through adjacent write lines and the transistor only passes the read current. This separation of read and write current paths has advantages, but scaling of field-switched MRAM is generally difficult. In ST-MRAM a write current is passed directly through the MTJ that switches the free layer magnetization by spin torque transfer [1,2], creating the additional requirement that the pass transistor be sized to support the required current.
Figure 1: Cell diagrams of a) toggle MRAM and b) 1T-1MTJ ST-MRAM under development. toggle MRAM switches with magnetic fields from current in nearby lines; ST-MRAM uses spin torque from the spin-polarized tunneling current.
The basic scaling argument for ST-MRAM is illustrated in figure 2. If the critical current density for spin-torque switching (Jc
) can be held constant, then compatibility with a minimum-size transistor improves with decreasing feature size, ?, since the critical current for switching, Ic
, will scale as ?2
while the saturation current, Id-sat
, of a minimum-size transistor scales as ?. However, there are a number of challenges to achieving this ideal behavior, some of which are described below.
Figure 2: Ic and associated ISW calculated for spin-torque switching of MTJ arrays assuming Jc can be held constant while scaling. Id-sat is assumed to be ~700 µA per µm of width, independent of node.
Significant results from several ST-MRAM demonstration circuits have been published, beginning with a 4-kb test vehicle in 2005  followed by many others including: a 2-Mb circuit and device data in 2007 , statistical data on 4 kb integrated arrays with 70×210 nm2
bits  and devices with perpendicular magnetization  in 2008, arrays integrated with 54-nm CMOS technology  and perpendicular bit switching in 2010 , and single-bit data for 20nm diameter perpendicular devices in 2011 . The continuous improvement reported in these papers, and many others, reflects significant innovation and progress toward the use of spin-torque switching in products.