LONDON – Leading chip manufacturer Samsung Electronics Co. Ltd. (Seoul, South Korea) has announced it has begun volume production of a 128-Gbit, 3-bit multi-level cell NAND memory using 10-nm class process technology. Samsung defines 10-nm class to be somewhere between 10-nm and 19-nm.
Samsung claims its chip has the highest physical density and the highest performance as it can move data at 400-Mbits per second using a toggle DDR 2.0 interface. Micron Technology Inc. recently announced a 128-Gbit 3-bit MLC NAND flash memory made using a 20-nm manufacturing process (see Micron launches dense 128-Gbit NAND flash)
Samsung started production of 1X-nm 64-Gbit MLC NAND flash memory in November 2012.
No details of the read or write performance, or the cycling endurance were provided by Samsung in a press release nor did the company provide a part number.
Samsung said it would use the 128-Gbit NAND flash memory to expand its supply of 128-Gbyte memory cards and to increase its production of solid-state drives with densities above 500-Gbyte for use in computers.
"The new chip is a critical product in the evolution of NAND flash, one whose timely production will enable us to increase our competitiveness in the high density memory storage market," said Young-Hyun Jun, an executive vice president of memory sales & marketing at Samsung, in a statement.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.