Flash storage has transitioned from a specialized solution for mobile devices with limited memory capacity to a standardized technology serving mobile, client and enterprise computing. The performance requirements imposed on flash storage are not trivial, and these requirements flow down to the electronic components used to assemble the device: CPUs, memory and clocks. The demands for small size, low power, high shock immunity and multi-million hour MTBF (mean time between failures) reliability are not simple to achieve, but are a good fit with today's MEMS clock generators capabilities.
In the 1990s solid state storage (SSS) technology was only used for specialized small-size storage applications such as digital cameras or USB data sticks. Today, the cost per gigabit of the technology continues to decrease to the point that SSS is now competing with and replacing hard disk drive (HDD) storage devices for both client and enterprise computing memory solutions.
SSS devices use nonvolatile memory as the storage media, which removes all moving parts, such as the magnetic drive that HDD storage has. SSS device architecture consists of an embedded processor controlling read, write, erase, encryption, and error detection functions on a network of memory blocks. The result is a memory storage unit that features faster access time, smaller size, lower power consumption, reduced cooling requirements, improved shock and vibration immunity and increased reliability.
SSS drives use NAND-flash memory technology to execute read/write functions to the storage media. The functionality of the NAND-flash memory is similar to the electronically erasable programmable read-only memory (EEPROM). The floating-gate transistor of the NAND-flash memory is the key component, as the floating gate minimizes the layout requirements of the memory cell, allowing a significant density improvement over other configurations.
NAND-flash performs read/write functions at a block level, with the typical block size being 4 kb (4,096 bits). This key SSS metric is referred to as the program-erase cycle (P-E cycle) and is used to compare the operational life of varying memory cells. NAND-flash configurations include single-level cells (SLC) 1 bit of information per memory cell, and multi-level cells (MLC) 2, 3 or 4 bits per memory cell. Memory cells can be configured to either maximize memory density, or P-E Cycle lifetime, the two specifications have an inverse relationship. Typical SLC performance is > 100K P-E Cycles/memory cell, two level MLC or MLC-2 performance is > 3k to 10k P-E Cycles / memory cell. A third configuration Enterprise MLC (eMLC) is now being offered which has the MLC-2 density but an improved P-E Cycle performance > 20k to 30k/memory cell.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.