The next major step forward in the electronics industry is the introduction of FinFET technology. The FinFET’s deployment circumvents fundamental performance and power characteristics planar transistors exhibited at 20nm and were hampering the value proposition of node migration. FinFET’s put the industry back on track. However, the combination of the new device types, 193nm wavelength lithography, resulting manufacturing-based rules, and materials physics are creating new technical and collaboration challenges.
A FinFET is a new type of multi-gate 3D transistor that offers significant performance improvements and power reduction compared to existing planar CMOS devices. In a FinFET, the gate of the device wraps over the conducting drain-source channel (Figure 1). This results in better electrical properties, providing lower threshold voltages and better performance as well as reductions in both leakage and dynamic power.
Experience at 28nm and 20nm has shown the critical importance of a vertical approach to collaboration in creating a complete enablement package for a new process node. This has become even truer for 16nm FinFET technology. To create a viable offering, all of the elements comprising enablement (process, cell library, EDA, and IP) must be optimized with respect to the other elements. As the manufacturing process evolves into a yielding node, the enablement package must track to the changes. Because of the mutual dependence, one element cannot be change without affecting the other elements.
Figure 1 – In a FinFET, the transistor gate wraps around the channel or “fin.”
While Intel started using FinFET technology (which they called “Tri-Gate”) at 22nm, most foundries are expected to adopt FinFETs at 16nm or 14nm. However, the backside metal layers will typically be kept at 20nm. Test chip tapeouts for 16/14nm FinFET processes started to appear in 2012, and early customer design engagements may start in late 2013. Challenges
Like any new technology introduction, however, 16/14nm FinFETs pose some design challenges. Most of these challenges are on the custom/analog side, but there are also issues that digital designers need to be aware of. This article looks at challenges from custom/analog, digital, parasitic extraction, and signoff perspectives.
In addition to FinFET-specific challenges, the 16/14nm process node has challenges that would appear regardless of transistor technology. These include:
- The need for double patterning (using extra masks) to get features to print correctly at 20nm and below
- Layout-dependent effects, which emerge at 28nm or above and become more problematic with each new process node
- Potential 50X or more differences in resistivity between top and bottom metal layers
- Electromigration increases with each lower process node
- Dozens of new and complicated design rules
- Complexity – how are you going to design and verify billions of transistors while meeting time-to-market demands?
Given all the challenges, Cadence expects that the EDA industry may collectively spend $1.2 billion to $1.6 billion for design tool R&D at 20nm, 16nm, and 14nm combined. In addition to handling FinFETs, design tools at 20nm and below must support layout analysis before final layouts are complete, colorization of layout features for double patterning, and accurate parasitic extraction and estimation. To handle the sheer size of advanced node designs, tools will need high capacity and fast run-times.