designers working with standard cells, and analog designers working on
IP blocks, will notice some changes with FinFETs. In particular, some of
the design strategies they have used in the past will no longer work.
This is because the intrinsic device characteristics are different.
planar transistors, standard cell designers can arbitrarily change
transistor width in order to manage drive current. With FinFETs,
designers cannot do this – they can only add or subtract fins to change
the drive current. Fins come in discrete increments – you can’t add
three-quarters of a fin. This issue is sometimes called “width
There are other issues not as well-known as width
quantization. For example, body biasing will generally be impractical.
The relatively large distance of the top of the fin (the active part)
from the bulk means that in order to modify the device voltage threshold
by biasing the bulk, one would need a very large voltage supply, which
is not available in 16/14nm processes.
Another challenge is a
side effect of something seen as a digital advantage – flat subthreshold
current (see Figure 2). This rules out analog design styles that are
based upon measuring current variations for fairly small voltage
variations between the source/drain of a planar device. The bottom line
is that the analog designers are going to have to come up with new
techniques to take advantage of FinFET device characteristics.
Figure 2 -- Comparing the electrical characteristics of a planar FET to that of a FinFET (sub-threshold current).
resistance and capacitance represent another challenging area for the
custom designer. As the device shrinks further on the horizontal plane,
and at the same time “rises” in the z-axis dimension, new coupling to
neighboring elements appears and creates additional parasitic
Starting at 20nm, Cgs (capacitance gate-to-source)
and Cgd (capacitance gate-to-drain) effects become an even larger
concern, and contribute to the Miller Effect that feeds the output of a
circuit back into its input through the parasitic capacitors. Also,
additional parasitic resistors in the source/drain area affect device
performance. What’s needed is a design methodology that very quickly
enables the designer to see the effects of these elements on the
performance of the circuit that is being developed.
Layout is not
without challenges either, although these are more “mechanical”
challenges than “intellectual” challenges. There are rules, and
designers must obey them. The problem is that there are so many rules
that drawing a piece of layout to follow them becomes a very tedious
exercise. Thus, layout tools must automate conformance to rules as much
One new issue is a side effect of how the fins are
made. A self-aligned double patterning (SADP) process, also called
sidewall image transfer, is used to create the fins. SADP requires that
all fins be aligned within a given fin area. This forces the layout
engineer to conform to a localized grid for each FinFET area, and it is
not always a simple uniform grid. This is in addition to the global
manufacturing grid for the “active” layer.
introduction of FinFETs into the custom design world comes with new
design challenges. Some are mostly intellectual challenges (how do you
take advantage of the new device characteristics), and some are
mechanical (conforming to design rules in layout). EDA can provide
assistance in both areas, and should certainly help automate any
mechanical aspect of designing with FinFETs.