a digital designer has access to automated, FinFET-aware tools and
characterized libraries, the main difference he or she will notice with
FinFETs is better power and performance characteristics. But digital
designers at 16nm or 14nm will also face new and more complex design
rules, double-patterning colorization requirements, and more
restrictions on access to cells and pins.
From an EDA methodology
point of view, 16/14nm digital technologies should be very similar to
20nm planar methodologies. But some added information and some new
capabilities are needed. Figure 3 provides a quick overview of the
digital implementation flow that’s required for 16/14nm FinFET
technologies (DPT is double patterning).
Figure 3 – 16/14nm FinFET digital implementation flow
placement, and routing should be double patterning-correct, meaning
that all metal topologies in the design are validated to be free of
double patterning conflicts such as odd-cycle conflicts or metal layers
that violate SAMEMASK rules in the LEF file. (SAMEMASK rules describe
special handling for nets that are masked by the same mask). One
particular step in floorplanning that is important is power planning.
16/14nm EDA methodologies must have the ability to validate that all
power routing is free of double patterning violations in relation to
other power routes as well as hard macros.
placement must be double patterning-correct, too. Standard cell and hard
macro pins, if colorized, must be separated in accordance to SAMEMASK
rules, meaning that metal shapes of the same color must not be in
There are a couple of ways to address potential
coloring issues in standard cells. One way is to insert spacing in
between violating metal shapes, while another way is to change the
orientation of standard cells to prevent or fix double patterning
conflicts (see Figure 4 below). All these considerations apply to
floorplanning and placement as well as optimization. A double
patterning-correct placement and optimization engine should ensure that
these steps are completed without introducing double patterning
violations, so the user does not have to manually verify color
Figure 4 – Double patterning-correct placement can flip or rotate a cell to avoid colorization conflicts
patterning rules apply to routing as well. What’s needed is a physical
verification engine that allows the tool to validate 16/14nm rules and
SAMEMASK rules while routing. After routing, designers should either run
an implementation-stage check on the routes to ensure adherence to
16/14nm double patterning rules, or invoke a signoff tool to run a
One important aspect of 16/14nm routing is the
difference in resistance of the routing layers. At 16/14nm, the
difference in resistance between a lower metal layer such as M1 or M2
can be 50X or more compared to higher metal layers like M7 or M8.
Therefore, routes that traverse a long distance should be routed using
higher metal layers as long as there are tracks available. For
short-distance routes or routes in highly congested regions, this
becomes less of an option because of the high usage of vias in that
route. An optimization engine should take routing layers into account in
order to leverage higher metal layers to reduce net delays.
short, from a placement and routing point of view, 16/14nm methodologies
are similar to 20nm methodologies. Both require double patterning
correctness. In 16/14nm FinFET-based technologies, there are additional
process rules that have to be adhered to by the placer and router, which
are all handled automatically.
Other aspects that are pertinent
to 16/14nm physical implementation include the size of designs, as well
as timing closure requirements. From a design size point of view,
16/14nm designs will be on average double the size of 20nm designs.
Design methodologies will have to be able to handle design sizes up to
200-500M instances at a full-chip level, and up to 10M instances on a
per-block basis. Because of this, technologies that are able to
significantly reduce peak memory and runtime in digital methodologies
will be important.
In addition, to address the increasingly
aggressive performance requirements of 16/14nm design, technologies like
clock concurrent optimization, which merge clock tree synthesis and
optimization into a single step, are able to improve design performance
in a big way.