Another unexpected, but much needed, change to the DDR4 specification was a new approach to the AC parametric test specification. DDR4 will be almost 50 times faster than DDR1, and the only way to achieve this speed boost is with changes to the AC timing specification. Without changes to the AC timing specification, there is just not enough timing margin to go around. DDR3 featured an unnecessarily large guard band that decreased the yield and required designs to be overly conservative. In today’s market, designers need every bit of margin they can get to gain a competitive edge. Excessive margin means more redesign to meet a tighter specification than is needed, and it can cause products to be late to market and more expensive—none of which memory companies desire.
Changes in the DDR4 specification tackled these issues head on, while system design and timing strategy are retained from DDR3. These complex changes are too numerous for the scope of this discussion. However, look for a future article on AC timing parametric specification changes from Perry Keller, JEDEC board member and Agilent Memory Program lead.
All of the DDR4 specification changes have been designed with three-dimensional silicon (3DS) stacking in mind. In traditional stacking, DRAM is stacked to decrease the overall footprint of the die; however, it has its limitations at DDR4 speeds. 3DS stacking can increase density, allowing up to eight devices to present as a single load. The 3DS architecture has one master DRAM and up to eight slave DRAMs stacked. The master DRAM provides a barrier to the slaves to keep the electrical load to a single point. 3DS is more pin efficient as well, since the 3DS rank selections are encoded. Because of the unique interface of a single-mode register, many commands are broadcast to all DRAMs simultaneously, such as resets. Other commands are still sent to individual die such as active, write, read, precharge and refresh. There is a performance benefit, both in timing and power, to creating a 3DS stack versus the traditional stacking methods, as not all DRAMs need a DLL disable, and buffering may be reduced and simplified.
Designers may feel overwhelmed with all the changes in DDR4. Attending one of the JEDEC workshops is the best way to receive in-depth technical knowledge from industry experts. JEDEC continually holds workshops, and they are listed at http://www.jedec.org/events-meetings. Another resource available from Agilent Technologies is the 2013 Memory Resource DVD for designers working on DDR and LPDDR. It contains demonstration videos, technical presentations, application notes and more. It can be ordered for free at www.agilent.com/find/hsd-achieve.
 Main Memory: DDR3 & DDR4 SDRAM, JEDEC article on DDR4 changes
About the author
Shamree Howard is the High Speed Digital Program Lead for Agilent Technologies, a role in which she works daily with professionals who preside on the board of
directors of standards committees such as PCI-SIG, JEDEC, and VESA, to
name a few. She has 10 years of experience in electronic test & measurement. Her unique focus in RF and digital designs gives her strong insight into the challenges engineers face in product development. Shamree’s technical background has allowed her to work side by side with Agilent experts as they define next generation products. She holds an Electrical Engineering degree from Bucknell University, and International MBA from the University of Denver.
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