Consider a simple configuration
with a trace directly over an uninterrupted plane. The signal travels
down the trace and the return signal comes back on the plane directly
under the trace. Conceptually, we can define a loop that the signal
travels as being the length of the trace from the driver to the
receiver, down through the receiver to the plane, back under the trace,
and back through the driver again. In simple terms, the area enclosed by
this loop would be the length of the trace multiplied by the height of
the trace above the plane (Figure 9-6). We call this the loop area of
the signal. The loop area is the area defined by the signal as it
travels down the trace and returns back to the source. (This is one
reason you need to know where the return signal is on your boards.)
loop area is important for this reason. From a practical standpoint,
for high-speed signals, EMI is related to loop area. If you want to
minimize EMI, you must minimize loop area. It’s as simple as that. Most
of us are intuitively aware that traces, even microstrip traces, routed
close to planes generally perform well from an EMI standpoint. That’s
because their loop areas are small. For the next few pages we’ll look at
illustrations where loop areas might get out of control, perhaps
Figure 9-6 Loop area, in this illustration, is 10 x length mil 2 .
Slots in Planes 1 Figure
9-7 is an illustration you will see three times in this book. There are
many reasons you don’t do what is shown there. The figure shows a trace
crossing a slot or discontinuity in the plane.
Figure 9-7 If a trace is routed across a slot, the return current must go around the slot, creating a larger loop area.
might cause a slot or discontinuity in a plane? Perhaps you have
finished the design and then your engineer comes to you with “one more
little part” that needs to be added. Making provisions for the routing
of this new part may involve a significant amount of rerouting of
already routed nets. But, perhaps you could just put a little slot in
one of the planes, route one or more of the new traces in that slot, and
finish the board quickly. Or, perhaps the plane has been partitioned in
some way, creating a discontinuity. Or, perhaps there is a special
component requirement nearby that results in a small discontinuity.
matter what the cause of this slot or discontinuity, if a high-speed
trace is routed over it, the return signal will be unable to travel
underneath that trace. When the return signal hits the discontinuity, it
must travel around it and then come back to its position under the
trace again. This trip around the slot or discontinuity creates a loop.
Since EMI is related to loop area, you have now created a possible EMI
problem where none existed previously.
Return Pathways Figure
9-8 illustrates a case where two boards are connected through a
connector. The signal between IC1 and IC2 travels through connector Pin
A. What provision should be made for the return signal?
use Pin B for the return signal, the loop area will be pretty small. EMI
performance should be satisfactory. But if we use Pin E for the return
signal, a significant loop will result. This loop may cause an EMI
This illustration highlights the importance of pin
assignments in our devices and connectors. It should also be noted that
some connectors are better than others with regard to their internal
paths. Some poorly designed connectors introduce loop areas even between
Figure 9-8 If provision is not made for a signal return (ground) through a connector, a larger loop area might be created.
9-9 illustrates another common problem. The figure shows a row of
clearance holes for pins for perhaps a component or connector. In Figure
9-9a and Figure 9-9b, a signal trace connects to one pin and the return
(ground) pin is on the back side. In Figure 9-9a the clearance holes
are wide enough to remove all the copper from the plane under the
connector or the device. The return signal, traveling under the trace,
must then travel around the copper void area to get to the ground pin.
This creates a loop that might become an EMI problem.
Figure 9-9 Good practice includes providing copper paths between through hole pins and assigning pins to minimize loop areas.
better solution is shown in Figure 9-9b. The clearance holes are
smaller, so that they do not remove all of the copper from the plane in
this area. Now there is a path for the return signal to travel between
the pins to the return (ground) pin. This approach is marginally better
than Figure 9-9a and results in a smaller loop area. And this
illustrates why it is usually preferable to provide a copper path on the
planes through all areas like this.
However, Figure 9-9c shows
an even better solution. If you have the flexibility to do so, it is
best to assign pins so that there is always a ground (return) pin beside
every signal pin. This provides the absolute minimum loop area for the
signal and its return, resulting in the best EMI performance.