All processor-based systems require some form of non-volatile memory to hold their boot code. When a processor starts up, it needs to load initial instructions in order to run the system’s applications. Parallel NOR flash memory has been widely used to store boot code because of its execute-in-place (XIP) capability, meaning the processor’s code can be executed directly from the NOR flash cells. Low-density NOR flash memory is inexpensive and plentiful, making it a popular choice for holding the bootloader. High-density NOR flash memory extends this functionality by allowing the system to store additional code, such as operating systems and applications.
The drawback though, is that NOR flash is a comparatively slow write technology and all writes require an erase first. This is basically true of any flash memory technology. However in the case of NOR flash, the write time for an individual cell may be fast, but the particular write mechanism used consumes a lot of power. This in turn means that it is not practical to write large amounts of data in parallel. NAND flash exploits the use of a different write mechanism to allow much faster writes for larger amounts of data. This is precisely what a host operating system would need for whatever file system it used.
Embedded system designers have known for a long time that a faster and more efficient way to run code is from random access memory (RAM), meaning it is no longer necessary to use the XIP feature of high-density parallel NOR flash memoryfor this operation. In these architectures, the contents of the high-density NOR flash are copied (or paged) into RAM for execution. RAM has faster access times than NOR flash memory for both read and write, and is often used as the run-time memory. In this architecture, parallel NOR flash is often replaced by serial NOR (SPI), which relies on the RAM for execution and has even slower write performance than an equivalent-density parallel NOR flash memory device.
In PC applications, hard disk drives (HDDs) are used as the storage medium for operating systems and application code, but HDDs are bulky and power hungry compared to high-density NOR flash memory. These characteristics, combined with reliability concerns, make them impractical for use in embedded systems despite the fact that HDDs have a very low cost per gigabyte (GB).
The managed NAND solution
A managed NAND device, such as a surface-mount solid state drive (SSD) in a ball grid array (BGA) package, offers an alternative data storage architecture that has improved performance, power savings and cost compared to both high-density NOR flash memory and HDDs. For further flexibility and reduction in pin count, a surface-mount SSD supports both the industry-standard ATA/IDE interface, yet can also be implemented on a general RAM memory bus (see figure 1).
Figure 1: Managed NAND flash memory devices like the parallel ATA (PATA) NANDrive deliver improved performance and higher speeds in compact, efficient form factors.
While not many new embedded processors feature a dedicated IDE disk interface, many of them do have a parallel address and data bus. The generic IDE driver can be easily ported to most embedded controllers, making it a seamless process to connect a surface-mount SSD to a microcontroller via the memory bus.
If we compare the available high-density NOR flash memory device capacities with the capacities of surface-mount SSDs, we can see that the surface-mount SSD comes into its own in capacities above 1 GB. Furthermore, if we examine the memory footprints of popular embedded operating system and application requirements, we can see that this is easily achieved with a single surface-mount SSD.
A typical WinXP Embedded implementation could require 2 GB of storage for operating system (OS), applications and user storage. An implementation with conventional WinXP would require a minimum of 8 GB, which would be very difficult to accomplish using today’s NOR flash devices.
Click table to enlarge.