All NAND flash memories continue to evolve the floating gate technology. But the basic cell structure has remained unchanged throughout several process generations. The self-aligned floating gate poly (SAP) process is still used by the three major manufactures.
Intra-gate poly to poly contacts are adopted by all manufacturers. In fact, two of the major manufacturers are still using the control gate (CG) and inter-poly dielectric (IPD) wrap around the floating gate (FG) configuration. Managing to keep most of the processes steps the same as the previous node is a great advantage for manufacturing because all the accumulated experience in process development is utilized to produce the new generation of devices. And yet every new node is a technological feat.
With every new technology node, the memory density (Mbits/mm2) increases and the process technology becomes more complex because all features on the die shrink but do not shrink proportionately with the same ratio.
Figure 2, shows a compound picture where the top image is the SEM cross-section along the Bitline direction of Samsung 21-nm TLC NAND flash and the bottom image is the corresponding topographical image at poly Wordline level. Figure 2 shows that the NAND string is consisting of 64 active Wordlines, two dummy Wordlines two select transistors at both end of the Wordlines and two contacts (Sourceline and Bitline).
Figure 2: Correlating SEM cross-section in Bitline direction with topographical image at poly-Wordline level. The topographical image shows the staggered Bitline contact layout.
The ratio of the length of the active Wordlines to the NAND string length is the overhead factor. Table 1 recapitulates some of the important features of last three Samsung NAND flash devices. This table puts in evidence the fact that the active cells are shrinking more than the string-select and ground select transistors and as a consequence the NAND string overhead has been increasing for the last three generations. As the active cells shrink the close distance between adjacent floating gates leads to parasitic capacitance which may result in a Vt shift. Samsung has done a major process change in 21-nm NAND flash devices to counter the parasitic capacitance issue as elaborated in Figure 3.
Table 1: Compiling some of the NAND cell features of last three Samsung NAND flashdevices. TLC designs make a huge impact on the memory density. As the technology scales down, the overhead seems to increase.
There are so many definitions for efficiency, so cannot comment on your number of 70%
In any case, there is a strong possibility that the next 1X generation will be conventional floating gate with wrap around IPD and only after that 3D NAND will come.
It's a game of chicken among the four manufacturers. Who will go quadruple patterning with floating gate, and who will go 3D with charge-trapping. TLC is just to delay this fairly terrifying choice. It's a good topic for a betting pool.
“MLC to TLC is not doubling…”
What matters for the storage is Mbit/ unit area.
One method is to use Triple-Level- Cell and the other is to shrink the memory cell and have larger memory density. If error correction and stability can be guaranteed than TLC is a viable option for increasing the density. Of course the endurance is another topic.
Memory products have low margin of profit so using EUV is not the first option. In the future, NAND memory will go vertical and have 3D structures. 3D structures will have a relaxed pitch and the vertical integration will help increase the memory density.
It is an amazing achievement by itself when you look at the SEM picture of a 64 bits wordline and triple level per cell. I think we have a tendency to overlook and take for granted this kind of technology marvel.
Next step will be 3D with charge trapping cell where the channel is made out of poly. That will give a huge boost to the NAND density with a relaxed design rules
The processing of 8 or more cycles of device layers cannot be considered the same cost as a single cycle. There is multiplied material consumption as well as processing time. So this 3D cost-effectiveness thinking is self-deceit.
This point hits home when, in the SADP flow, the "spacer dep", "spacer etch" and "mandrel etch" were tagged as separate cost items in the cost stacks. If we applied this to 3D NAND specific process, we would have cost stacks 16 or 32 x higher!