This 21-nm NAND flash has abandoned the silicide process and opted for tungsten metal gate. This transition is not new; it has already been done in many DRAM products. However, depositing tungsten on poly is not a straightforward process; several interface treatments have to be done, which are described in the report.
Tungsten metal gates leads to controllable air gaps, which mitigate the parasitic capacitance. Other challenges including choosing a suitable inter-poly-dielectric (IPD) layer. The IPD thickness affects program/erase speed and magnitude of read current and the quality of the dielectric layers has a direct impact on the endurance of the flash device.
A thinner of IPD layer will increase the capacitive coupling between the control gate (CG) and the floating gate (FG) and generate a higher read current and a faster program erase mechanism but can also compromise the retention capability. So a tradeoff has to be made.
The IPD layer composition in 21-nm NAND flash is still the same as the previous generation but the individual layer thicknesses are modified. Also, in the Wordline direction, the aspect ratio for poly 2 gap-fill is greater than five. Here, too, Samsung has come up with new process techniques. Samsung’s 21-nm 64 Gbit TLC NAND flash technology has a process flow similar to its previous generation but with an enhanced process capability. It remains to be seen if the next generation 10-nm class 128-Gbits TLC NAND flash will manage to prolong the existing process flow or will take the next big step of fabricating 3-D NAND stacks.
This point hits home when, in the SADP flow, the "spacer dep", "spacer etch" and "mandrel etch" were tagged as separate cost items in the cost stacks. If we applied this to 3D NAND specific process, we would have cost stacks 16 or 32 x higher!
The processing of 8 or more cycles of device layers cannot be considered the same cost as a single cycle. There is multiplied material consumption as well as processing time. So this 3D cost-effectiveness thinking is self-deceit.
It is an amazing achievement by itself when you look at the SEM picture of a 64 bits wordline and triple level per cell. I think we have a tendency to overlook and take for granted this kind of technology marvel.
Next step will be 3D with charge trapping cell where the channel is made out of poly. That will give a huge boost to the NAND density with a relaxed design rules
It's a game of chicken among the four manufacturers. Who will go quadruple patterning with floating gate, and who will go 3D with charge-trapping. TLC is just to delay this fairly terrifying choice. It's a good topic for a betting pool.
Memory products have low margin of profit so using EUV is not the first option. In the future, NAND memory will go vertical and have 3D structures. 3D structures will have a relaxed pitch and the vertical integration will help increase the memory density.
“MLC to TLC is not doubling…”
What matters for the storage is Mbit/ unit area.
One method is to use Triple-Level- Cell and the other is to shrink the memory cell and have larger memory density. If error correction and stability can be guaranteed than TLC is a viable option for increasing the density. Of course the endurance is another topic.