Design How-To

# Improving peak current-mode control

Forced to over design

The analysis shows that the input power, which is calculated at the
minimum input line voltage, increases from 6.81W to 8.12W, which is a
16.1% increase. This forces power-supply designers to over design the
power stage. **Figure 3** is a plot of V_{OUT} versus the output current (I_{OUT}) of a power supply operating with peak current-mode control.

**Click on image to enlarge.**

*Figure 3. Peak current-mode control V*

_{OUT}vs. I_{OUT}.**Novel implementation of peak current-mode control**

To improve the performance of peak current-mode control, a novel method of biasing up the peak primary current as seen across the current sense resistor was developed, line current limit feed-forward. In the flyback converter topology we can take advantage of the transformer auxiliary winding, which is used to provide bias power to the controller. Referring to

**Figure 4**, while the main flyback switch is on, Q1, the voltage on the auxiliary winding is negative and proportional to the rectified line voltage (

**Equation 7**).

(7)

Where: naux is the number of turns on the flyback primary (Np) divided by the number of turns on the transformer auxiliary (naux) winding.

**Click on image to enlarge.**

*Figure 4. Flyback converter with feed forward.*

The input to the PWM QR pin of the controller is a current mirror. As the voltage on the auxiliary winding goes negative, a current (IQR) proportional to the input rectified line voltage is mirrored by a gain of 100 (

**Equation 8**), and injected on to the current sense resistor to offset the current sense voltage (VCS

_{OFFSET}). The current into the QR pin is set with a resistor RFF.

(8)

The first step is to force the peak current at the maximum V

_{IN}to produce the same input power as we calculated at the low-line input (

**Equation 9**). We do that by subtracting the current overshoot as a result of the propagation delay from the input power at the minimum input line.

(9)

Therefore, the required current limit feed-forward as seen across the current sense resistor is (

**Equation 10**):

(10)

To inject a 0.0634V offset voltage onto the current sense resistor, we need to calculate the voltage on the transformers Auxiliary winding (

**Equation 7**), selecting IQR in a range of 1 mA to 4 mA. For this example, we used 2 mA. Now we can calculate the required RFF (

**Equation 10**).

(11)

The current injected on the current sense resistor (Rsense) is the IQR current divided by the current mirror gain of 100 (

**Equation 12**):

(12)

The I

_{CS}current is injected onto an external resistor (

**Equation 13**) that is series with the CS controller pin and the current sense resistor (R

_{SENSE}). The result is that the current sense resistor has a biased that is proportional to the input line voltage. This turns-off the peak current earlier, forcing the input power at the minimum input line to be approximately equal to the input power at the maximum input line.

(13)

**No over design**

Peak current-mode control in conjunction with line current limit feed-forward eliminates the requirement for power supply designer to over design the power stages. This reduces the cost, as well as being a low-complexity solution for power supplies and battery chargers.

**References:**

1. Abraham Pressman, Keith Billings, Taylor Morey,

*Switching Power Supply Design, Third Edition*, the McGraw-Hill Companies, April 17, 2009.

2. Christoph Basso,

**"The Over Power Phenomenon,"**How2Power TODAY, October 2010.

For more information visit:

**www.ti.com/power-ca**.

**Terry Allinder**is a principle applications engineer for Texas Instruments Power Products Division. He has over 30 years of power electronics experience as an Application Engineer and power supply designer for military applications. He received his BSEE from California Polytechnic University, Pomona. Terry can be reached at ti_terryallinder@list.ti.com.