LONDON STMicroelectronics has three design wins for its 28-nm fully-depleted silicon on insulator (FDSOI) manufacturing process.
Carlo Bozotti, CEO, told financial analysts here that in the first quarter ST has signed up two customers for digital ASICs for communications networking using the process and has a third customer that plans to address high volume consumer electronics. Bozotti did not provide the names of the customers but said that Globalfoundries Inc. (Milpitas, Calif.) has signed an agreement to bring up the process and act as a second source.
The ultra-thin body and buried oxide (UTBB) FDSOI planar process is claimed to have advantages over other manufacturing process variants, such as bulk planar CMOS and FinFET CMOS in terms of trade-offs between performance, power consumption and manufacturability. One concern has been the cost and availability of the specialized SOI wafers but ST claims that the simple nature of the process compared with FinFETs makes the total cost of production advantageous. ST has pioneered the process, although major semiconductor IDMs and foundries are working on the premise that bulk CMOS at 20-nm will be quickly followed by FinFET manufacturing at about 16- or 14-nm. Intel introduced the first FinFET process at 22-nm.
FDSOI was available for pre-production from its Crolles 300-mm wafer facility in December 2012. However, the company has been faced by a potential chicken-or-egg problem. Concern was expressed that some customers would hold off from signing up for the process until they saw evidence of a supporting ecosystem and foundries and EDA and software IP providers such as Cadence, Synopsys and ARM declining to commit until they could see ST had customers for the process.
"We now formally have a second source available to us and to a number of our competitors, but not all," said Bozotti.
Jean-Marc Chery, chief manufacturing and technology officer, told the analysts that ST products based on FDSOI will have an advantage over products produced in either bulk CMOS or FinFET process. "And we are winning ASIC business thanks to the performance-power and because its a simpler process than FinFET. The yield learning curve is the equal of bulk CMOS," he said.
Chery said ST would be able to meet customer ramp up of FDSOI products from its Crolles 300-mm wafer fab near Grenoble, France and that Globalfoundries would be in position to help with volume production at its Dresden fab in 2014. Chery showed the audience that the next node 14-nm UTBB FDSOI will start prototyping in 2014 or 2015 to be followed by 10-nm UTBB FDSOI in 2016 or 2017.
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