Contemporary IC designs have advanced quickly from 65 and 45 nanometers, down to 28, 20, and below. This progression to ever smaller geometries has brought significant challenges in achieving timing closure to meet production deadlines and market windows. Engineering teams often struggle to efficiently perform late-stage ECOís to satisfy their design objectives. There are many problems that combine to make this a particularly difficult task:
A big obstacle to closing timing is due to the fact the signoff timing analyzer and the ECO tool employ different engines. This practically guarantees there will be timing differences between engines, making convergence difficult. To compound the problem, commercially available ECO tools do not consider physical information when determining buffer insertions and routing changes. Submitting a modified circuit to signoff STA may solve a problem in one area, but introduce a problem somewhere else.
Too many iterations
Poor convergence forces engineers to perform many iterative loops though the ECO process to achieve timing closure. These iterations are not only time-consuming, but may not linearly progress to a final solution.
Difficult physical issues
Complex chips are typically quite dense, making late-stage routing changes extremely difficult. Moreover, many chips contain several power domains. Specific buffers are needed for routes to traverse alternate power domains, further complicating the routing issue.
Excessive buffer insertion
Power is always a consideration in chip designs. Excessive buffer insertion can increase a chipís power consumption, making it less-competitive, or missing its power goals completely.
Figure 1: Conventional timing ECO flow
As result, the only efficient way to achieve a solution to these problems is to consider these issues simultaneously.