LONDON – Xilinx Inc. (San Jose, Calif.) has said that it will use the 16-nm FinFET manufacturing process of Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) to build the industry's highest performance FPGAs under a collaborative work program called FinFast.
The two companies are bringing employees together to be part of a "one-team" approach to optimize the FinFET manufacturing process for Xilinx's Ultrascale architecture, Xilinx said. The FinFast program is expected to deliver 16-nm FinFET test chips in 2013 and first products in 2014. The companies said they will also make use of the CoWoS [chip on wafer on substrate] 3-D IC manufacturing flow to produce multi-die systems.
It was announced that Intel would make FPGAs for Altera using its 14-nm FinFET manufacturing process back in February 2013. At the time Altera also stated that it expected to have FPGA products in 2014. Xilinx's FinFast crash program may be seen as a reaction to that announcement. Xilinx said the products from the FinFast program would be announced at a later date.
"We are committed to TSMC as the clear foundry leader in every dimension, from process technology to design enablement, service, support, quality, and delivery," said Moshe Gavrielov, CEO of Xilinx, in statement.
"We are committed to working with Xilinx to bring the industry's highest performance and highest integration programmable devices quickly to market," said Morris Chang, chairman and CEO of TSMC, in the same statement. "Together we will deliver world-class products on TSMC’s 20SoC technology in 2013 and on 16FinFET technology in 2014."
TSMC recently announced that it is accelerating the production schedule of its 16FinFET process to 2013 (see TSMC stats FinFETs in 2013).
Xilinx has told TSMC of the high-end FPGA requirements that it needs included in the FinFET process. Further co-optimizations are planned for the TSMC process technology and the UltraScale architecture and its supporting design tools. UltraScale is the FPGA architecture, developed to scale from 20-nanometer planar, through 16-nanometer and beyond FinFET technologies, and from monolithic through 3-D ICs.
Yes 16 node is really 20 node transistor density (both transistor pitch and metal pitch are same as 20) at higher wafer cost.
It makes no sense. Cost per transistor goes up (Moore's law goes backward)
Plus if that was not bad enough it is too costly to build and validate design IP for 2 nodes with the same transistor density.
This is why Altera, Cisco, Micro Semi and i hear likely another another left for intel. Intel''s 14 nm will have a real 14nm metal system and a real 14nm transistor density
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