Editor’s note: This work was first presented at the 2012 IEEE
International Electron Devices Meeting (IEDM) and appears here courtesy
of the IEEE. For more information about IEDM 2013 (Washington DC;
December 9-11), click here.
Recently, we have suggested highly manufacturable and reliable 3D NAND flash cell called “SMArT”, which is intended to minimize both stack height and word line resistance. Because the storage node of this cell is charge trap nitride, its device characteristics were far different from conventional floating gate. In this paper, the key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.
Nowadays, the NAND industry immediately faces the unprecedented scaling limitation of the conventional FG NAND cell. Even though some cost effective 3D NAND flash cells such as BiCS, TCAT and DC-SF have been proposed, the increasing vertical height with word line (WL) stacks makes it hard to implement transition to mass production because of their inherent issues of poor data retention and enormous process complexities as well. In this paper, our highly manufacturable and reliable 3D NAND flash is briefly introduced, and its key cell characteristics are compared with our FG cell of 2y node in chip level. Finally, several key technological challenges of 3D NAND flash will be discussed to overcome some barriers in near future.
Figure 1: TEM cross-section image of 3D NAND string and schematic drawing of SMArT unit cell. Key features of SMArT cell
Memory stack of the SMArT (Stacked Memory Array Transistor) scheme is shown in Figure 1. In this scheme, the stack height is minimized by inserting ONO layer in the plug. In addition, the WL height can be reduced by applying low resistive tungsten (W) and merged cell array architecture.
Minimization of total WL stack height was firstly considered, because multi-stack etching technology is key huddle of 3D NAND process integration and it will seriously impinge on the manufacturability. By refreshing the blocking oxide of ONO memory stack at metal gate replacement step, the SMArT scheme belongs to the “gate-last” process, providing better reliability. Our TiN gate MANOS cell technology  is applied without gate direct patterning, which produced etching damage at the gate edge and seriously degrades the reliability in 2D cell. Comparison of device characteristics A. Program-Erase Window
Program-Erase (PE) speed of SMArT cell is compared with 2D FG in Figure 2, where the program speed is much faster but the erase speed is much slower in spite of field enhancement of GAA structure. Despite the smaller PE window, the NAND operation window is not insufficient to MLC or TLC, because program saturation is much larger than FG and cell to cell interference is nearly negligible.
Figure 2: Comparison of program-erase characteristics of 2y node FG cell and 3D CTD SMArT cell.
Figure 3: Comparison of total interference of 2D FG and SMArT cell as SK Hynix technology node. B. Cell Vth Distribution
Cell Vth distribution is one of the most attractive features . The interference of CT 3D cell is nearly negligible at ~30nm gate space as shown in Figure 3. The cell Vth distributions of MLC 3D NAND are compared with our 2y node in Figure 4, where the distribution widths are as small as over ~30% at each level, because of its well known interference free nature.
Figure 4: Comparison of cell Vth distribution 2y node FG and SMArT cell. Figure 5: Program disturbance modes of 3D NAND flash cell array (left) and difference of inhibited conditions (right). Figure 6: Sub-threshold swing difference of string selection transistors between 2D FG on Si-sub and SMArT with poly-Si channel. C. Program Disturbance
Program disturbance of 3D NAND is far different from FG. All kinds of 3D NAND to date have two or more strings in a block. This architecture makes new program disturbance mode as shown in Fig. 5. The “Y mode” program disturbance has more severe VDS condition by Vbl(=Vcc) than the conventional X mode in FG. In addition, the leakage current of drain selection transistor (DSL) is not easily suppressed due to the weak sub-threshold nature of poly-Si channel as shown in Figure 6.
Recently, we proposed a few approaches to suppress the program disturbance: keeping higher DSL Vth, adopting the negative DSL bias, and inserting dummy pass WL’s. Especially, the dummy WL condition has to be paid special attention, because high channel boosting can generate the hot carrier at the edge WL region by high lateral electric field. This induces that the channel potential of the edge does not boost up when the edge cell (WL0) is programmed (Figure 7). This phenomenon can get worse in 3D cell because of the floated body effect, which increases the channel potential of selection transistor region during programming and it can induce much worse disturbance characteristics. Therefore, the dummy WL bias and number have to be carefully controlled. Fig.8 shows dramatically improved program disturbance characteristics of X and Y mode by applying optimized conditions.
Figure 7: Channel boosting simulation at inhibited condition of each wordline programming pulse.
Figure 8: Suppression of Program disturbance fail bit by applying optimized conditions proposed previously.