Editor’s note: This work was first presented at the 2013 International Memory Workshop and appears here courtesy of the IEEE.
Charge-trap flash memory has been successfully productized in high volume for several technology generations. Two-bits-per-cell MirrorBit charge-trap technology has been the industry benchmark for NOR flash for more than a decade, spanning six generations of scaling. More recently heterogeneous fharge trap (HCT) NAND flash as well as embedded charge trap (eCT) NOR flash have been developed. The planar cell structures will enable continued scaling of these charge-trap technologies, while new architectures such as 3-D charge-trap flash will emerge and further extend the density-growth trend.
Floating-gate (FG) cells were utilized when the flash memory industry emerged in the 1980s. While FG cells are still commonly found today, the charge-trap flash has been scaling effectively, and has captured a significant portion of the market that requires high intrinsic reliability, small cell size, and good performance at elevated temperatures. Two-bits-per-cell MirrorBit flash is now ubiquitous in high-density parallel and serial NOR applications. 45-nm MirrorBit technology is in volume production today with 8-Gb chip, which is the highest-density monolithic NOR flash in the market (see figure 1). Meanwhile, 32-nm MirrorBit cell has been demonstrated and will enable even higher density of monolithic NOR flash . For NAND applications, industry’s first manufacturing-ready, charge-trap NAND technology called HCT NAND flash has been developed.
Figure 1. Die photo of 45-nm 8-Gb MirrorBit NOR flash product.
For SoC products with ultra-fast read access time, eCT flash is being integrated with an advanced logic process. In this paper, technological advancements and key attributes of each of these charge-trap technologies are presented. MirrorBit NOR Flash
Spansion has been successfully scaling MirrorBit NOR flash for over ten years, with 32-nm development currently in progress (see figure 2). With its virtual-ground architecture, MirrorBit technology is relatively immune to the gate-to-drain shorts and single-bit charge loss/gain seen in FG NOR technologies . Key features of MirrorBit technology include buried bitlines, dual-poly memory gate, salicided wordlines, and design architecture optimized for fast access time and program speed. Charges are stored in localized regions of the non-conductive, charge-trap film near each of the two junctions, thereby providing two-bits-per-cell operation.
Figure 2: Scaling trend of MirrorBit and floating-gate NOR cells.
MirrorBit memory array utilizes a highly symmetric pattern of straight wordlines and bitlines on plain active area (see figure 3). Shallow trench isolation is not utilized in the core. At the 45-nm node a bitline trench is formed following poly patterning to achieve robust programming behavior while maintaining good short-channel characteristics. After filling the bitline trench with HDP oxide followed by CMP, a second layer of poly is deposited and etched to define the wordlines. CoSi is then formed on the wordlines to attain low resistance. Contacts from the buried bitline to a M1 strapping layer are patterned in a relaxed wordline space. One bitline contact is placed every 16 cells; that provides significant advantage in effective cell size over the traditional FG NOR array, which requires one bitline contact for every two cells. TEM cross sections of MirrorBit cells are shown in figure 4.
Figure 3: Top-view illustration of MirrorBit memory array.
Figure 4: TEM’s of 65-nm (a and c) and 45-nm (b and d) MirrorBit cells in bitline and wordline directions. Bitline trench is a new feature introduced at the 45-nm node.